985681095613121110984215613121110984215613121110984219867561312111098421561312111098421542356131211109842173652141391514111012654321121323810965454151416171918111111S86StorEcOut.6'StorEcOut.5'StorEcOut.4'....S374SCKSOC'SCKSOC'S374S374S374S374S374S374S374S374S374S374S374TRTRTRTRDCFERRTDCFERRTTRTRDCFERRTError Correction GeneratorS280S280S135S135S86DCFERRToacaTTRRRRRfedccdefcdeffedcPPPPoacaTTRRRRRfedccdefcdeffedcMemory Control01EODD0GbXEROXFileProjectDesignerRevDatePageRRRRRRRRRODDTTEVNTRPS280S280PTRRRRRRRRRRODDTTEVNRRRRRRRRRODDTTEVNTRPS280S280PTRRRRRRRRRRODDTTEVNStorEcOut.0'StorEcOut.1'StorEcOut.2'StorEcOut.3'RRRRRRRRRODDTTEVNRRRRRRRRRODDTTEVNH4.01H4.03H4.05H4.09H4.11H4.13H4.15H4.07H4.02H4.06H4.07H4.10H4.03H4.11H4.14H4.15H4.04H4.05H4.06H4.07H4.12H4.13H4.14H4.15H4.08H4.09H4.10H4.11H4.12H4.13H4.14H4.15H4.00H4.03H4.05H4.06H4.09H4.10H4.12H4.15H4.01H4.02H4.04H4.07H4.08H4.11H4.13H4.14D0mem01.silGNDGND171281162212212318GenSyn0GenSyn1GenSyn2GenSyn3GenSynXS86S86GenY'GenY'GenXGenXGenXGenYGenY'GenYGenXGenXGenPhase0DCFERRTS86H4InputPEH3IParity192311.553.564.564.559595911.5ThackerNote: Storage card invertsNote: GenPhase0 => GenSyn0,1,2,3,X = 1(pullups on page 12)17b16b17b18c17c19c18c15bc15cc15dc15ec15fc15gc15hc15ic15jGNDb19ab19bc16cc16bc16ac14cc14bc13bc13cc13jEdgeClock'aTRHGiTRHGiGNDe1ce1dPUaPUbS04S04StorEcOut.7'data and check bits.GenYGenX.7/18/80CG -G G G t O d OO dOA ; >>;>;>;>;>>KA r$A r$KKA ] r$A# r$K @t ; :; !V;A|A :W:W:W :W!:WX:"$= $=!$9=#%@$=$=$A$:W<:W<:<:<:!:!:W!:W!>>>;>;>;!>;!>!>!pyK9xVp<y$x.Gr9/:;t>GGGr>;Gr:Gr#GrNGNXGGrNXG GrGr |X! Y> ZZ [v \ ] ^ _ a t^ rZ$ @ rZ$Z$  re$|[v\ t_d$c$b|$a`$`C$_'$^ $\$_' 9$]$U:]|$y|[v[v:`N$:]|r$5W]!Y$Y]$Y$][$ 9tdn 9WN{$LB$]LB]$!Lf$5W|PZPJ$U:P&$yN!N!:S|N$:P&r$Q 9$O$P$Q$R$T $U&$VC$W_$ J K M N! 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Replaced with S00 a15a, and added MC1StartMC2' as input to MC1Active.4) Added MC2PS12' by replacing f3 (S74) with S175 (pg 19). MC1PS12' is used instead of PStore12' at a1.13 (pg 20).2) (pg 13,15) Changed i9 from S74 to S175. Relocated i9's functions to i10. Added MOBounds as R.05 during R_Pipe operation.Changes from RevH to RevI (5/9/78)1) (pg 20) h3.9 was MC2HoldIfSNE0, is now MC2StartXport' after passing through the 8T09 at h9b (used as a driver).2) Renamed signal MC2TestSNE0 to MC2HoldIfSNE0 (essentially, these two signals have been coalesced into one).3) Added test points.4) Added comments on Vee bypass and -10V supply changes to D0memplatforms.silChanges from Rev I to Rev J (8/12/78 - C. Thacker)1) Renamed signal TP055 GateALUParity, and connected it to E079 (pg 10)2) Latched signal StorAccessType in S374 at h4f (pg 15)3) Removed MC2XferWord and MC1XferWord from a5.11 and a5.12. Connected a5.11 and a5.12 to a5.13 (pg 16). Notethac signal MC1XferWord is no longer used on this card, so E006 is free.4) Removed -10V supply components on D0memplatforms.silChanges from Rev J to rev K (10/8/78 - C. Thacker)1) Changed h7.12 from MC1WriteMem to MC1WriteMemSlow (pg13). This signal is generated at platform a16 (pg12).2) Changed platform a16 to 20pins to make room for MC1WriteMemSlow (pg12).3) Added capacitors on SloMapRAS' and SloMapWrite' (platform c5, page 12).4) Changed a9.12 from MC1Task.3 to MC1Next.4 (pg15).5) Changed i7.1 from PUb to Referenced (pg15). This requires changing PROM i7 to revision E.Current PROM Revisions:f14 (Single/Double errors): Da4, a3, a2, b3, b4, c2, c3, d2, d3, e3 (MC1 Sequencer): Eg3, g1, h1, h2, i2 (MC2 Sequencer):Di7 (Fault):b11 (Ftype, Pipe):DEChanges from Rev K to rev L (11/1/78 - C. Thacker)1) Signal clkOutputReg is now clkOutputReg' by removing S37 at h6a (now free) page 13.There are no prom changes in this revision.2) b10.1 (pg15) was Disableb10, is now GND. Also removed Disableb10 from SPLAT i1 (pg 12).Changes from Rev L to rev M (12/9/78 - C. Thacker)1) Changed platforms c5 and i1 - removed capacitors and changed values.2) Changed the generation of clkOutputReg' (pg 13). This signal is now one cycle wide, rather than being a qualified EdgeClock.3) The input to h5g (pg 13) is PreRovAd', not EnRowAd'. This board requires an ALU board of rev M for proper operation.There are no prom changes in this revision.Note: Rev M = Rev GaChanges from rev Ga to rev Gb (7/18/80 - CPT).Gb7/18/801) Added 16 FICAPS for MK4116 chips (VDD and VEE)2) Added glitch suppression capacitor adjacent to h7 (on MC1WriteMemSlow - 100pf).3) Changed interlock logic on page 18.9x@pEtGUBGU:GU*:GU GUGUGMGMGGxC;;t9*p]MG;t@*@r]tfd1cQhUa"_n]L\/YX52TfS4sV}P"MrKnJQHME2D4IB8@p?4H=8;P29o7J6PK452^pt  8s#O  O1P2/V,P+-[*2(G'O%x#+"O .C;p@G@9t19S93& NgT12345678911121314151617101819ABCDEFGHI1-100101-20020pins: A16pins: B14pins: C22pins: D24 pins: ENote: The short vertical lines indicatefilter capacitor locations.D0DateRevDesignerProjectFileXEROXd0memlayout.silThackerMemory Control Board LayoutCSL16pins REVERSED!!!4116typical of MK4116: F4116411641164116411641164116411641164116411641164116411641164116PLATPLATPLATS20934279342793427S6425S09S241S260S260S04S00S374S04S64S00S240S240S00S649342793427S374S374S64S37S374HM7603S189S64S6425S09S280S280S280S135S009342793427S374S37S138S257S257S189S135S374S374S86S86S280S280S280S049342793427S374S374S374S374S374S374S00S257S37425S0925S0993427S374S04S374S10S374S374S135S138S374S374S25725S0925S09S240S00S10S175S37S00S374S374S374S13593427S374S25725S0925S099342793427S37425S09S00S374S374S135S138S374S374S25725S0925S09S2409342793427S374S374S374S37S37S748T09S240S30S74S151S374S00S08S280S280S28093427S64S32S08S5193427S175S74S74S74S74S8625S09S280S280S280S374S3747/18/80GbSPARE(143 Places)100pfABC100pf.................Note: Pinx marked withhave 470ohm pullup resistors to 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