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Vb! b! rc> rc> da( c$ +] V] ] r^ r^ d\ _n$ +Y> VY> Y> rZZ rZZ dXE Z$ +T VT T rU rU dS V$ +PZ VPZ PZ rQv rQv dOa R$ +K VK K rM rM dJ M$ +Gv VGv Gv rH rH dF} I4$ +C VC C rD  rD  dB  D$8e\<\<\8]8]:[:^Q$8eX!8Y>:W(:Y$8eS>$= $?WpA$A*V$I|'<IXJtt*IGOgY61456439810564311314121156432710159215142375691110121413151413101112765234191119867542319234765101112151413PageDateRevDesignerProjectFileXEROXRosenEODD0Control BoardCTask.0CTask.1CTask.2CTask.3TPC-A.0TPC-A.2TPC-A.325S09QTRRDBQTRRDB25S0925S09QTRRDBQTRRDB25S09SBRRCK25S09HiPri.2HiPri.1HiPri.0ALUA.01ALUA.02ALUA.03TRS374S374TRTRS374S374TRAPCTask.0APCTask.1APCTask.2APCTask.3HiPri.3ALUA.00TPC-A.1InCTsk.0InCTsk.1InCTsk.2InCTsk.3SCKSOC'ClockInCTsk'GNDS374h18bh18ch18dh18eh18fClockAPCTask'i18bi18ci18di18ei18jAPC_TPC25S09SBRRCK25S09QTRRDBQTRRDB25S0925S09QTRRDBQTRRDB25S09ClockTPC-A'e18be18ce18de18ee18fQTRRDBQTRRDBQTRRDBQTRRDBAPCTask.3APCTask.2APCTask.1APCTask.0NxtCTsk.0NxtCTsk.1NxtCTsk.2NxtCTsk.3E'RRSBS157S157S157S157S157GNDSelAPCTask'TPC-SelHiPri'g17bg17cg17dg17eg17fGc<<<YY3X3Y2X2Y1X1Y0X0TTSRRRRRRRRSS>=C;>I4BC;BI4FC;FI4KmC;Km):4)9/Km)Km)JQ/F)F)E/B(lB(lAm/>(l>(l<GrOtGOtGGr Gr#Gr:Gr>;GrGGrGx>;t/:9.Gr$py0WOtG9xpy J r$Er$A&$<r$<$tHC?4:JQAm<*>/;$*:;$-=/|: ): )9*t=*)>)=v*tA*@*^D$*:@ $*C*G/D$*:D$-Fm/|C)C)A*tFm*EP*^H$*:D{$"sF$"sK&$/I$*:I$-J/|Gv)Gv)FY*tJ*I*^L$*:H$*K*9*:7$/:7$+*:; $$*:7%$)|6<)5 *t8e+W7lAmEJQ"sF"sB"s>/:K&$/:F$/:BB$/:=$HI$UDXI{$yH|GvCGvDXLN$DXI{r$DtIDEPHE-$UDXE $yH|CCCDXH_N$DXE r$H@$UDX@$yH>C>DXCN$DX@r$Dt@D <H=$HBB$HF$HK&$"sKmEKKmKFKBK>G|4E t8DX8e$UDX;$H8B$yDX8Br$EP|4Ft8Et6$=6 G6$IX6G6$Et:+I4+D+@P+;,s9 :9 :8 $ :9 $=6$EtKEtGEtCEt>F9 ::46P385$5$+9$$6 $]|5 ]43t7IVJG$G$I|FY]FY]E=3tI3HK$G$C$C$EP|A]A]@3tEP3D4Gf$C_$VFmVA?$?$@|=v]=v]$:$:$$:{$V=r7 r7V$sHsCs?4s:8 29$V9$ ;P 2|776t;P:4y=f$V9^$ 2=$V=$ ? 2|yA$V=$ 2Bf$VBf$ D4 2|@@?tD4CyFI$VBB$ 2F$VF$ H 2|E=E=D tHGyJ$VF$E$J $H$G$C_$D{$@ $>$:{$;$; @P D I4 VH r$ VD{ r$ V@ r$ V; r$I4 D @P ; 6P|24V4$V8$$ V4$+V4$t7l rI rEP r@ r 9 7l<pH_sI$sH9$sD{9$sD$C :?{@-$@ 9$s;9$s;$;  xH D4!V? ;PJtp$ Vt#s#%"D=l=3=!=D O;&3>>=|X=>>>;>;==;CD4AA>t>@$@O$@O$@$@P$@P$$>> y=| =X>X>X> > = = C D4 A A >ty>@$@$@$@k$@P$@P$>>@=|=>>>>==CWD4WAtAt>t @> @$@ $@ $@2$@P]$@P $>O>=|=>>>t>t=;=tCD4AA>t >A@,$@$@$@$@P$@P ]$IXlEtH;|DX$:WA$1s $;t$1st 1s $1sy $1s $1s $1sA $1s $1s!z $1s% $:W$:W$;t$;t y$1s!1s1sO1s 1sl1s321sC;C;CODXAAkA A" $% $$" $V| ! !! Vt!#l#" #$:W $;td$ ",$#1s@ $=- $$#$9#9$a^_#le$cQ)dnzdnzfe4;dn:dn:cQ4;_:_:^kff5{X|7X|-V-X3W%XXXVX|TTUU:T!tW%V$U V$y%|T ]T Z&N$ Vr$ X|y$ tX sX X| $&X !YQ/:|UZ/:UZ3S.T.R2S%:X| $&VCy$&tV 6P|UZ5WYr$9Y$y5W\$5WY$U6 tY7Y8|UZ8UJ$5tUm6tZrX5H|bbccb5W]|$5{a$5t_n4|\:4\8t_n5W]$:4]$:4|Z8t^.5Wa$5{e$5c4|`w:4`w8tc5Wb$:4b$:4|_Z8tb:Wd'$<dn:W_$<_s|c>sc>Va+b+`wa/tW2Um%:|a(`w$_Z$a%:b!%:b!%:_ZVeC$)d' 9$f`$]!k\AZA]!]]Z_ $9` $9f` $rbr]!rZ9^ r$rd' $$r`$Ur[$r[$!V[$]!Vc $VtfVaV^f`^Q]fdcQ(b55b55]+dn+_:W|Z:W_Zte9;W 3W_ $6tW$95U&$d_n&Wc6td6t`6t\W1s |X dt d d d d d d3 | ; X t     $ ] $$ 9 $ dtO|X$t$d$+$|X 9tr $z $] $A $$ $ $ $ $]$$$$ l $$ $$$ k3O VO |tVtV ; ;tdWdtdt 9 @ r$ ]$ $$ $ t  $9$: k |trp rt : !V   k2?Wp|  ; : VV  $ $ $t :9$",| &W % "s;"s;$e &$$t%&W$*: $U y$ G$U $$2 O #GOgPageDateRevDesignerProjectFileXEROXRosenEODD0Control Board15Change HistoryRev E to Rev F1) The Clock Drivers on page 12 were moved from c1/d1 to a18/b18 to eliminate waveform distortions due torefelections at the connector that caused false clocking on some boards. This necesitated moving the TPC-Amultiplexor (page 1) from b18 to g17, and the Wake-up encoder S00 from a18 to c06. The wake-up lines now havelong stubs on this board. The HiPri register was also moved up next to the S00 encoder (from e01 to d06).2) The S30 at g6 that makes BPC-Ref' (page 10) had Breakpoint' added to it. This prevents the BPC-Refill trapfrom occuring when the sucessor of a breakpointed instruction points to an instruction which has NextInst or Nextopspecified.3) The trap location for Fault and BPC refill were reversed by changin the term on CS-A.11 from BPC-Refill' toStartFault' (S20 at a6 on page 9). Faults trap to 1, BPC refill traps to 0. This forces a nextinst/nextop which bothBPC refills and Faults to hit the fault handler rather than the BCP handler.4) The EPROM sockerts were changed to allow 2716s or 2758s to be plugged in. This removes all dependancy on the +12/-5supplies for booting, and allows a 1k boot program. This change also affected the bit tested to determine end ofboot load (from APC.00 to APC.05, thus affecting TstAPC.00 on page 3 and page 11)5) A new Clock was added for the EOM board (ROS printer). This clock, EomClock, is a 35ns (nominal) squarewave, witha clock driver. See page 12.6) Final testability changes were made, they include: a) A new signal, TesterDisable which is an independent pullup resistoron a new plat at e2 (page 11). This signal enables the S241 on page 3 which allows tester control of TstAPC.05, EnableBootProm, EnabCIA. b)another new signal, also an independent pullup (page 11) which allows tester to force CSOp to set.c) an S51 at b1 now lets the tester turn off the oscillater with a new signal-ExtClockEnab'. This signal is pulled up on thee3 plat instead of ExtClock'. c)the clock generator flip flops can be initialized by the InitClk' signal, which is pulled upon the e2 plat.7) a minor improvement was achieved by eliminating the S32 at d6. Only one section was used (SRData, page 10) andan unused S32 section was available in the e16 S32. d6 is now empty3/8/78 Brian Rosen1) The chip enables for the TPC rams (control sections on pages 1 and 2) were run through an S241 controlled byDisableTester to allow tester control of APC inputs3) The select input of the data in mux for bits 32:35 of the control store (page 8) was modified to run throughanother S241 gate to allow tester control of the data input to these 4 RAMs.2) The Run/a signal was run through another tester controlled S241 gate to allow tester control of the EPROMs (page 11)4) A new pull down resistor was added to the e2 plat (page 11) creating the signal TesterPullDown. This is the controlinput to the tester S241 (page 3)D0csChanges.silRev F to Rev G 4/17/78 Brian Rosen5) The signal ChipSelect' (an input to all 2147 RAM chips, pages 4:8) was broken up into 3 separate nets, eachj fed froman S410 gate at i6 (page 3, nets CsChipSel'a, CsChipSel'b, and CsChipSel'c)6) An adder, S283 was added between CIA and the TPC ram inputs (page 1) to make the return address CIA+1 (carriespropogate throug 4 bits only). New chip is at c1.7) The clock term for CTD (page 13) needed to have MemInst' as an input. Added a new gate (e15a) to make this term.Rev G to Rev H 9/8/78 Brian Rosen1) The Abort' term on ClockTPC-A' (g15.11) page 2 is erroneous, it was removed.2) The Cycle1 term on RunningT2 came very late for some qualifier terms. It was changed to Cycle0Feed' thus cuttingtwo gate delays3) The Complement of the actual BranchBurp signal is needed for new clock driver scheme (see note 4 below). Addedan invertor to BranchBurp using a4.3 and a4.4 creating BranchBurp'. The signal from b6.3 (page 9) had it namechanged to BBurp'4) Clock Drivers (page 12) were changed from S32s to S37s. This changed all inputs on a18, b18 and c5.5) Cycle0Feed' is too late. The S37 that created this signal (page 12) was deleted. Cycle0Feed' now come from a5.8this affected the name of the signal at b3.5 (was EarlyCycle1, now Cycle0Feed')This EarlyCycle0 is also used on a10 (page 9) and i2/g2 (page 13). The next revision (I) will remove some of these loadsFor now, they are all Cycle0Feed'Rev H to Rev I - 11/18/78, C. Thacker1) The register ByteCode is added (f2,d1,e1, pg13). This register holds ALUA[6:13]' for one cycle following NextInst, so thatthe bytecode can be written into TPC by the subsequent RETURN. This allows task switches between bytecodes.2) The signal SRData (buffered H2.15) has been deleted. This requires a backplane change (pg 4,5,10).3) The branch logic on pg 10 is changed to add IntPending (in place of Disp999), QWO, and a SpareBranch.4) The signal NxtInNoTsk' is generated in c6a (pg2). This signal is true if a task switch will NOT occur in the RETURN following aNextInst. This signal determines the source of APC data during NextInst.5) The signal NxtInstRTN' is generated in i17c (pg2). This signal will be asserted by all RETURNs following NextInsts, and will cause ByteCode+1 rather than CIA+1 to be written into TPC.6) The function decoder on pg 10 is changed to bring out SpareF', and rename DispCnt' and DispClr' to be IncMPanel' and ClrMPanel'7) The generation of RUN(pg11) is different. The feed signal from d4.6 is latched, RUN is generated on platform e2.(NOTE: e2 is changed to 18pins). PwrBoot' is generated in e16d.8) CSOP (pg10) is clocked by clockT2' (used to be called ClkFault', pg 12).9) EarlyCycle1 (pg 12) was added to reduce loading on Cycle0Feed'.10) Clk1 is brought to the backplane (E12 -> E112) so that a delay can be inserted to reduce the width of RamClock.11) a5.13 (pg 12) is connected to InitClk' rather than to PUa.12) Stack overflow logic is added on pg 13.13) NewInst (used to be an F) is generated on pg14.14) Added TimeOut branch condition (pg10) and brought R-ParErr and CS-ParErr to the edge connector (pg 13).Changes to revision Ga (2/18/79 - CT)1) Changed all plats to 20 pins on logic diagrams to cause ROUTE to do no trace cuts.2) Added synchronizer on TimeOut (pg 10)3) Changed D0Off' to E53, ClrMPanel' to E55 (pg 10).4) Added spare IC's in positions f1, g1, h1, i1, h6.Rev Ga to rev Gb (3/8/79 - CT)1) Added g3b, d1c on pg 14. This change keeps NewInst from occurring when the first microinstruction of a bytecode is aborted.Gc7/18/80Rev Gb to rev Gc (7/17/80 - CT) Eliminated signal PwrBoot', changed RFB register clocking (pg 11).CG -G G G GrOtGOtGGr Gr#Gr:Gr>;GrGGrGx>;t/:9.Gr$py0WOtG9xpy Jttg9fidkcnbj9an_s^ 9]5n\vZL9YwXqWQ9VuUm9TQ|S4wRxP}O|N9MrLD g9IoH39EPoD4L9Fw9BwAm!$ptKm$9?x>K99+939k%9OU9 2(9 5;t@$9 4 O9<p?WtcGOhu12345678911121314151617101819ABCDEFGHI1-100101-20020pins: A16pins: B14pins: C22pins: D24 pins: ENote: The short vertical lines indicatefilter capacitor locations.D0DateRevDesignerProjectFileXEROXModule Layout- D0 Control StoreRosenD0csLayout.silCSL18 pins: FOSCS74S00S04S20S10S00S37S00S51S74S64S37S260S00S37S37S00S74S30S00S00S32S10S10S10S10S00S11S08S20S11S04S10S74S74S10S280S280S280S280S02S10S64S74S74S20S00S00S20S74S10S51S51S374S374S374S374S374S241S240S240S374S374S374S374S374S241S2412147214721472147214721472147214721472147214721472147214721472147214721472147214721472147214721472147214721472147214721472147214721472147214721472147S374S374S240S30SPARESPARESPARESPARESPAREPLATPLATPLATPLATPLATPLATS283S85N123S175S175S174CSd4S138S138S251S175S15725S0925S0925S0925S09S158S158S158S158S158S158S163S163S163S189S189S189S253S253S253S253S253S253S253S253S25725S0925S0925S0925S09S157S157CSc12CSg12(123 Total)S04S747/18/80GcCG -G G G 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