*start*
04800 00024 US 
Date: 1 April 1980 2:05 pm PST (Tuesday)
From: Thacker.PA
Subject: D0Mods
To: Vest.PA, Anthony.ES, Kakita.ES
cc: Thacker.PA

Changed 4/1/80:  added control item 4, terminal interface items x and y.

This is a list of all changes that must be made to the D0 multiwire boards as
of 3/28/80.

-----------------
CONTROL (starting documentation is revision Gb, 3/8/79):

1) The platform in e2 must be modified from the state shown in the 2/19/79
drawing:
	1) remove the 220 ohm resistor from pin 9 to pin 12.
	2) remove the 10 uf. capacitor from pin 10 to pin 11.
	3) add a 1k 1/4 w resistor from pin 8 to pin 12.
	(This change disables the signal PwrBoot' on page 11).

2) There is an error on the loading chart.  location a5 should be S74, not S04.

3)	lift f3.9
	lift c2.11
	add wire c2.11 to f3.5
	add wire f3.9 to f3.8
	(This changes the clocking of the RFB register, pg. 11)

4) Add a 33ohm 1/8 watt resistor in series with a5.8.  This is best done by lifting
the pin and soldering the resistor from the IC lead to the hole in which the pin
used to go.  (This change reduces noise on Cycle0Feed').

------------------
ALU (starting from revision Ga, 12/9/78):

1) Chips b19, b18, and b17 have 33 ohm 1/8 watt resistors in series with pins
3,5,7,9,12,14, and 16.

2) The signal R.14  is cut from pin E127, and also cut at e17.2, and a wire is
added directly from E127 to e17.2 on the back side of the board.
(This reduces crostalk in this line).

-------------------
MISC (Starting from revision Gb, 10/14/79)

Note that revision Gb includes the "timer change" of 10/14/79.  The
documentation includes the add-delete list to update revision Ga to revision Gb.

1) lift pin: e18.5
add: e18.5 to e18.7
(This change causes base register accesses made by memory instructions to
interlock)

--------------------
MEM CONTROL (Starting from revision Ga )

1) A 100 pf. capacitor is added between E48 and ground (E40).  (This change
reduces crosstalk on MemSetFault)

2) Signals Idata.00 - Idata.16 are pulled up to +5 via 470 ohm 1/4 watt resistors
mounted at the edge connector.

3) (The following change causes LoadType to be inhibited only if R transport
will actually take place)
lift pin: e1.10
add: e1.11 to c1.12
add: e1.13 to c1.13
add: c1.11 to a1.2

4) (The following change corrects an error in the generation of LDisableMC1'
and AdvancePipe')
lift pins: b1.1, b1.13
add a 1k resistor from b1.1 and b1.13 to b1.14 
lift pins: f2.5, f2.3
add: f2.5 to f2.3 to b1.8

5) (The following change corrects an error in the generation of
MC2DisableMC1t')
lift pin: f2.2
add: f2.2 to f2.7

---------------------
MAINT. PANEL (Starting from revision Gb, 6/11/79).

1) R35 (was 22K) is now 4.7K.

2) R25 (was 1K) is now 470 ohms.

3) R36  (?? 1/2 watt) is 470 ohm, 1/4 watt.

4) Need some sort of quick-disconnect for the NiCad battery.
----------------
UTVFC (starting from revision Ga)

1)	lift pin c16.5
	add e18.8 to d17.5
	add d17.7 to c16.5

2) Pin 15 of all four terminal connectors at the rear of the board must be
connected to GROUND.

3) To set the speed identification for 20mhz, wire e1.4,5, and e1.11 to e1.3 (hi),
and wire e1.6 and e1.7 to e1.8 (ground).

-----------------
RDC (Starting from revision Gb, 9/3/79).

Note that revision Gb is a manual modification of revision Ga (the Multiwire
version.  The changes below are in addition to the revision Gb changes).

1) The a3 prom must be changed (to revision X).

2)	lift i13.5
	lift h14.1
	add e3.11 to e3.10
	add i13.5 to h14.1
	(This keeps the format sequencer inactive during seeks).

3)	lift d11.13
	add d11.13 to e12.10
	(This clocks a flip flop on pg 12 with RamClkFeed1 rather than
EdgeClkFeed1).

4)	lift b4.1 (Hi1)
	add b4.1 to a15.10 (IRun)
	(This change turns off sector wakeups if the disk is not delivering
clocks).
------------------
ETHERNET (Starting from revision Ga 4/12/79).

add: i14.5 to i16.18 (this wire was omitted from the Multiwire boards)
-------------------
Terminal Interface (Starting from revision Gb 8/22/79).

1) Lift: 3F.13
add: 3F.13 to 3F.9

2)  Add a 1uf solid tantalum capacitor in parallel with the 1000uf 25v electrolytic
capacitor that filters +5 (the electrolytic has enough inductance that the +5
regulator may oscillate if the 1uf cap is omitted).

3) The 7-wire terminator plug assemblies made by RichLong (and possibly
others) have seven terminating resistors; there should be only six.  The extra
resistor is between pins 13 and 14.  Remove it.

--------------------
BACKPLANE

Add 5ft coax cable delay line per <IBIS><VEST>DelayLine.sil

Add a 150 ohm, .25 watt resistor from J16.172 to J16.151 (pullup for IOAttn')
------------------
96K STORAGE BOARD

Add U-169 pin 16 to U-168 pin16.
------------------


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