DOLPHINMICROASSEMBLER9 October 1981byEdward FialaXerox Palo Alto Research Center3333 Coyote Hill RoadPalo Alto, California, 94304Filed on:[Indigo]D0Microassembler.PressSources on:[Indigo]D0Microassembler.DmThis manual describes the Dolphin microassembly language, based upon the 16 May 1979 release of theDolphin Hardware Manual, and hardware changes up to the release date of this manual.This manual is the property of Xerox Corporation and is to be used solely for evaluative purposes. No partthereof may be reproduced, stored in a retrieval system, transmitted, disseminated, or disclosed to others inany form or by any means without prior written permission from Xerox.Н$╒ОJ╠pНОE≈ Н$║О>&qТ· Н)pО9TrН%SО5⌡qНО0;Н!кО.*Н !О,НyО$НsТ─НёП&НyО#G НёП%НyОHТ╩ПKТ╪НyОдТПSrНyО≥sТ▐ПbТ░НyО8ТёПEТєП(НyОЄТПDrЄy╒8cJ▌^Dolphin MicroAssemblerEdward R. Fiala9 October 19812TABLE OF CONTENTS l.Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.Assembly Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.Debugging Microprograms . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.Cross Reference Listings . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.Conditional Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 8.Simplified Parsing Rules . . . . . . . . . . . . . . . . . . . . . . . . . .11 9.Statements Controlling Assembly . . . . . . . . . . . . . . . . . . . .1210.Forward References . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1311.Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1412.Repeat Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1413.Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1514.Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1515.SetTask Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1616.Assembling Data for RM . . . . . . . . . . . . . . . . . . . . . . . . . .1817.Assembling Data Items In the Instruction Memory . . . . . . . .1918.General Comments on Instruction Statements . . . . . . . . . . .2019.RM and STK Phrases . . . . . . . . . . . . . . . . . . . . . . . . . . . .2220.Cycler-Masker Phrases . . . . . . . . . . . . . . . . . . . . . . . . . . . .2321.A Phrases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2422.B Phrases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2523.ALU Clauses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2624.Memory Reference Instructions . . . . . . . . . . . . . . . . . . . . .2725.RM Interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2826.Standalone Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3027.Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3028.NextData and NextInst . . . . . . . . . . . . . . . . . . . . . . . . . . .3229.Placement Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . .3430.Tasking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .3531.Microcode Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3632.Recent Hardware and Assembler Changes . . . . . . . . . . . . . .36ЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuН жО^оtТ÷Н⌡ОZґrТ└НПSН<Н⌡ОXБНПMН<Н⌡ОWНПPН<Н⌡ОUMНПIН<Н⌡ОS┌НПLН<Н⌡ОQ╦НПPН<Н⌡ОOМНПLН<Н⌡ОN#НПLН<Н⌡ОLXНПGН<Н⌡ОJ█НПLН<Н⌡ОHцНПTН<Н⌡ОFЬНПOН<Н⌡ОE-НПRН<Н⌡ОCcНПSН<Н⌡ОA≤НПNН<Н⌡О?нНПJН<Н⌡О>НП?Н<Н⌡О<8НП@Н<Н⌡О:nНПJН<Н⌡О8ёНПMН<Н⌡О6ыНПSН<Н⌡О5НПSН<Н⌡О3CНПOН<Н⌡О1yНПGН<Н⌡О/ўНПOН<Н⌡О-ДНПNН<Н⌡О,НПQН<Н⌡О*NНПKН<Н⌡О(└НПLН<Н⌡О&╧НПLН<Н⌡О$ННПNН<Н⌡О#$НПAН<Ъ xЇ!62зFу$Dolphin MicroAssemblerEdward R. Fiala9 October 198131. PreliminariesThe machine now called the Dolphin was at one time called the D0, so these two names are usedsomewhat interchangeably within this manual.The Dolphin microprogramming language is implemented as a set of definitions on top of themachine-independent assembler Micro; Micro is an Alto program, so assemblies are carried outeither on an Alto or on a Dolphin emulating an Alto. The assembly language is based upon themachine description in the 16 May 1979 release of D0 Hardware Manual and hardware changesthat have occurred up to the release date of this manual.Files referred to in this manual are as follows:DocumentationWhen Using the Assembler[Indigo][Indigo]D0Manual.PressD0Lang.McD0MidasManual.Press[Maxc2]D0Gotchas.PressMicro.Run[Maxc2]MicroD.RunMicro.PressThe assembly language is defined by D0Lang.Mc. I have tried to make D0Lang.Mc and thisdocumentation complete, so you should not need to refer to the Micro manual or study D0Lang forfurther details, except where noted here.Micro flushes Bravo trailers, so you can use Bravo formatting if you want to. However, the crossreference program, MCross, which is expected to produce primary microprogram documentation,does not handle Bravo trailers. Also, line numbers in Micro error messages may be more difficultto correlate with source statements because of the line breaks inserted by Bravo's hardcopycommand. I advise against Bravo formatting for these reasons.I recommend use of Gacha8 (i.e., a relatively small fixed-pitch font) for printing program listings,and use of Gacha10.Al for editing source files with Bravo. The smaller font is desirable becausesome statements will be long, and a smaller font will allow you to get these on one text line. Bravotab stops should be set at precisely 8 character intervals for identical tabulation in Bravo andMCross.The two relevant lines in USER.CM for BRAVO are:FONT:0 GACHA 8 GACHA 10TABS: Standard tab width = 1795You will probably want to delete the other Font lines for Bravo in User.Cm.I also recommend that you read the hardware manual through once or twice before programming;you will be referring regularly to the figures and tables in the hardware manual until you becomeextremely familiar with the machine.ЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuНЇО^оtТ÷НЇО[]rТ▀Т▄ПGНЇОY⌠ТП,НЇОV!ТІПOТЇ НЇОTVТўПPТ╞НЇОR▀Т■П.Т∙П/НЇОPаТ╒П.ТёН+НОPjЧоОPаН.`ОPjЧыОPаН4эОPjЧ▌ОPаНЇОNЖТП9НЇОK└П0НyОHцvН#уНyОF$sН#уН:ОDд Н'GН:ОCcН#уН:ОBН'GНyО@║Н'G Н:О?A НЇО;РrТмПWНЇО:'Т└Т┘ПHНЇО8]ТП)НЇО4КТ·ПNТ÷НЇО3 Т╧П7Т╨П$НЇО1UТ≈П&Т≤П;НЇО/▀ТТТУПOНЇО-юТП>НЇО*NТ╒П?ТёП%НЇО(└ТїП3Т╗П.НЇО&╧Т┘ПBТ├П#НЇО$НТрП\ТсНЇО#$НЇО╡ТП0НyОПsНyО░НЇОArПKНЇОоТ≤П\НЇОТ°П<Т²П%НЇО:ТП$Ъ ЇС=ГWDolphin MicroAssemblerEdward R. Fiala9 October 19814Note: All arithmetic in this manual and in Dolphin microassembler source files is in octal.2. Assembly ProceduresA microassembly is accomplished as follows:Micro/L D0Lang Source1 Source2 ... SourceNThis causes the source files "D0Lang.Mc," "Source1.Mc," ..., "SourceN.Mc" to be assembled. Theglobal switch "/L" causes an expanded assembly listing to be produced on "SourceN.LS"; if "/L"is omitted, no listing is made. The assembler also outputs "SourceN.Dib" (intermediate binary andaddresses), "SourceN.Er" (error messages, which are also printed on the display), and "SourceN.St"(the Micro symbol table after assembling SourceN.Mc).In other words, Micro assembles a sequence of source files with default extension ".Mc" andoutputs four files whose extensions are ".Dib", ".Er", ".Ls", and ".St". The default name for theseis the name of the last source file to be assembled. Direct output to particular files as follows:Micro Sys/L/B D0Lang Source1 ... SourceNcauses the four output files to be "Sys.Ls", "Sys.St", "Sys.Dib", and "Sys.Er." These four files areused as follows: The ".Ls" file is the assembly listing which you will usually not want to create--theMicroD listing file mentioned below is generally of greater value. The ".St" file is a dump of thesymbol table at the end of assembly; it can be used in subsequent assemblies to recreate theassembly environment, as discussed below. The ".Dib" file (Dolphin intermediate binary) is the filethat will be processed by MicroD later. The ".Er" file contains error messages and other assemblyinformation.A summary of local and global Micro switches is as follows:Global:/LProduce an expanded listing of the output/NSuppress .Mb file output/UConvert text in all source files to upper case/OOmit .St fileLocal:/RRecover from symbol table file/LPut expanded listing on named file/BPut binary output on named file with extension .Dib. Default symbol table (.St) and errorlisting (.Er) to named file./EPut error listing on named file/SPut symbol table on named file/UConvert text in named file to upper caseAssemblies are slow--it should take about 7 minutes to assemble a 400010-instruction program.INSERT[file] statements, described later, can be put in source files so you don't have to type asmany source files on the command line. However, this will slow assembly because each INSERTmakes a separate call on the directory lookup code (about 1 second), but all names on the commandline are looked up at once. A better shortcut is to define command files to carry out yourassemblies.ЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuНЇО_rТЦП.ТДП#urНЇОZ tТ÷НЇОVўrТП+НyОSЛsП*НЇОP·rТ∙П<Т√П#НЇОNсТ≥П<Т П"НЇОMТ▄Т█ПLНЇОK>Т▌ПbНЇОIsТП5НЇОFТжТвПSНЇОD7Т▌ПUТ▐НЇОBlТ╡ТЁПLНxО?sТП(НЇО:ШrТ▓ПOТ⌠НЇО90Т│Т┌ПWНЇО7fТ≈Т≤ПPНЇО5⌡ТяП6ТрП&НЇО3пТ└П<Н0юО3yЧО3пТ┘Н67О3yЧcО3пН>+О3yЧфО3пНЇО2Т▓Т⌠ПLНЇО0;НЇО,иТП;НxО*sН\Н/П)Н\О(└Н/Н\О'Н/П.Н\О%|Н/НxО#GН\Н/Н\О!цН/П"Н\О ?Н/Т▒ПJТ▓Н/ОчТН\ОZН/Н\ОжН/Н\ОRН/П(НЇОrТсП#ТтП#ОvsОrНЇО╣Т╟П^Т╠НЇОЙТ÷ПHТ═НЇО Т─П;Т│П&НЇОUТьПVТыНЇО┼ Ъ .ЇC=Г[х<Dolphin MicroAssemblerEdward R. Fiala9 October 19815After obtaining an error-free assembly from Micro, you must postprocess the .Dib file with MicroDto transform it appropriately for loading by Midas. This is accomplished as follows:MicroD SysMicroD displays a progress message while churning away, and requires about 60 seconds to processa 400010-instruction file (longer when large listings are produced). The local "/O" switch directs theoutput to the named file rather than to the last-named input file (default extension .Mb), so:MicroD NewSys/O Sysputs the output of MicroD for the input file Sys.Dib onto NewSys.Mb.In this example, there is only one input file for MicroD (Sys.Dib)--it is also possible to assemblesource files independently using the symbol table (.St) file produced by Micro to establish a basispoint for further assemblies, thereby reducing assembly time. For example, you can build aGlobalDefs.St file as follows:Micro/U D0Lang GlobalDefsThen do all further assemblies as follows:Micro/O/U GlobalDefs/R Sys/B Source1 ... SourceNMicroD GlobalDefs SysPreassembling D0Lang and GlobalDefs in this way might save 10 seconds of assembly time.MicroD can relocate code in IM (but not in any other memories). On very large programs, such asthe system microcode, it is possible to proceed as follows:Micro/U D0Lang GlobalDefsMicro/O/U GlobalDefs/R Source1Micro/O/U GlobalDefs/R Source2 ...Micro/O/U GlobalDefs/R SourceNMicroD Sys/O GlobalDefs Source1 Source2 ... SourceNwhere Source1 ... SourceN may assemble IM locations but must not assemble any RM locationsreferenced externally--internally referenced RM locations may be defined in Sourcex, but this has tobe done in a way that avoids assignments that conflict with other sources. In other words, forwardand external references are permitted only in instruction branch clauses, so everything else must bepredefined in GlobalDefs.St or at the beginning of a source file.One advantage of this method is that Source1 ... SourceN can be independently maintained withouthaving to reassemble the entire system for every change; another advantage is that it avoids symboltable overflow--the current system microcode is near to overflowing at present. However, manychanges to GlobalDefs will necessitate reassembling everything, and when everything is reassembledthe total assembly time will be about 9 minutes rather than 7 minutes.Note that you do not need to do anything special in your source files to declare labels which areexported (defined here, used elsewhere) or imported (used here, defined elsewhere). Micro assumesthat any undefined branch symbol is meant to be imported (but gives you the list just so you cancheck), and MicroD assumes that all labels are exported. MicroD also discards all but the lastНЇОf╙uТ─Н!цrН4]ТНHYОfЯuНЇО_rТ┼П2Т▀П/НЇО]KТПUНxОZ┼s НЇОW;rТ▄Т█ПQНЇОUpТ│ОTЦsОUprП_НЇОSіТрПTТс НxОPДsТНЇОM∙rПDНЇОJ#Т·ПXТ÷НЇОHYТ║ПcНЇОF▌ТчП[НЇОDдТНyОBsНЇО>ЁrП*НyО;РsП0НyО:▒НЇО7BrТЕП+ТФП,НЇО3пТ┤ Т┬ПVНЇО2ТП;НyО/DsНyО-ДНyО,┐НyО+"НyО)аНyО(`П3НЇО%rТЄПIТ╣НЇО#GТ└ПKТ┘НЇО!}Т▐ПAТ░П"НЇО╡Т▒ПdНЇОГТПAНЇОuТ┴Т┼ПKНЇО╚Т▄П@Т█П#НЇОЮТ╧П,Т╨П2НЇОТ┼ПCТ▀НЇОKТПFНЇОыТ║П8Т╒П)НЇОТ┘ПGТ├НЇОDТ⌡П8Т°П(НЇО yТ╪П*ТҐП5 ФЇ 2=Г]ыDolphin MicroAssemblerEdward R. Fiala9 October 19816definition of a name (e.g., the symbol "." is defined in every file as the address of the lastmicroinstruction).MicroD produces up to seven output files, depending upon the local and global flags specified onthe command line. The name for these files is determined as discussed earlier, followed by theextensions given below (i.e., Sys.Mb, Sys.Dls, ... , SysOccupied.Mc):.MbBinary output--data for memories and address symbols for use when debuggingwith Midas; this file is produced unless the global /P switch appears on thecommand line..DlsListing file always produced--it contains the Executive command line and allstrings printed on the display while MicroD is running (i.e., progress informationand error messages); this is followed by a table showing the number of freelocations on each page of IM, and by a list of data and address symbols in eachmemory (which can be modified by various global and local switches discussedbelow)..RegsRegister allocation listing produced if the global /R switch is specified; it lists innumerical order RM locations and address symbols associated with each..CSMapControl store map produced when the global /M switch is specified; when MicroDinput consists of a number of modules (i.e., of .Dib files), the .CSMap file willshow for each page in the control store (i.e., each page in IMX) the number ofwords in each module allocated on that page and the number of free locations inthe page..CSChartA file showing which .Dib file contained the instruction at each real address, sortedby real address; this is produced only when the global /E switch is specified and isintended for hardware debugging with a logic analyzer..absDLSA file giving the correlation between real and imaginary IM addresses, sorted byreal address; this is produced only when the global /H switch is specified and isintended for hardware debugging with a logic analyzer.Occupied.McA file which can be assembled to reserve all locations occupied by the currentimage. It contains IMReserve declarations for every location into which MicroDhas placed an instruction. The intent is that this file be used when buildingoverlays to run on top of the current image.A summary of the local and global MicroD switches is as follows:Global:/AList only absolutely-placed IM locations/CConcise listing--list everything except octal contents of IM/DDebug--print a large amount of debugging information/EProduce a .CSChart file (of Every location)/HProduce a .absDLS file (useful for Hardware debugging)/IIgnore OnPage/KKludge enable--suppress LoadPage consistency checking/MProduce a .CSMap file/NNo listing--IM contents and other memories are not listed/OProduce the Occupied.Mc output file containing IMReserve statements for all locations filledЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuНЇО_rТшПJТэНЇО]KНЇОYыТ°П8Т²П(НЇОXТЁПXТЄНЇОVDТПEНxОS<НТ©П4ТюНОQqТщТчП4НОOїТНxОL·НТМП)ТНП#НОJтТєПFТ╔НОI ТщТчП/НОG?Т╒ТёПCНОEtТаПLНОC╘НxО@║НТєПMТ╔НО>вТПFНxО;оНТ└Т┘П=НО:ТІП,ТЇП%НО89Т╞П3Т╟НО6oТ Т⌡П;НО4єТНxО1°НТ│П,Т┌П)НО/яТ└Т┘П<НО.ТП6НxО*ЪНТїТ╗П?НО)4ТєТ╔ПDНО'iТП6НxО$a НТ≥ПNНО"≈Т╗ПOНО лТсП.ТтНОТП,НЇО░П@НxОнsН\Н/П(Н\ОJН/П<Н\ОфН/П4Н\ОBН/П+Н\ОЎН/П6Н\О:Н/Н\ОІН/П5Н\О2Н/Н\ОўН/П9Н\О*Н/Т┴П8Т┼П$Ъ РЇ=Г]>Dolphin MicroAssemblerEdward R. Fiala9 October 19817by MicroD/PPrint only--supresses all MicroD actions and just lists all .Dib files/RProduce a .Regs file/SList symbols for all memories (except Version, RVRel, Disp, IMLock, and IMMask, whichare consumed by MicroD). /N prevents /S from listing IM symbols/TTrace--print a trace of calls on the storage allocator/XExternal--allow references to unbound symbols in the .Mb fileLocal:/AList only absolutely-place IM locations--overrides global setting/CConcise listing--overrides global setting/LList everything--overrides global setting/NNot IM listing level overrides global setting/OOutput file/VVersion number/ZSpecifies scratch file to use instead of SwateeGlobal switches are usually specified on the command line as "MicroD/nmo Sys/O ..." but MicroDaccepts "MicroD Sys/O ... ~/nmo" as an alternative. This alternate form is useful with commandfiles because it allows varying switches to be specified at the end of the command line. In otherwords, if one has prepared a command file Foo.Cm containing "MicroD/n Sys/O ... ," the "~"feature allows variant switches via "@Foo ~/nmo" to the Alto Executive.Only one of the /A, /C, or /N global switches, which control additional material printed in the .Dlsfile, can be meaningful--when none of these switches is specified a verbose (/L) listing will beproduced. The /A, /C, /L, and /N local switches overrule the global switches for a particular file.The ordering of these is as follows: /L is most verbose; /A prints less IM information than /L; /Cprints all other memories but not IM; and /N prints neither IM nor other memory information.MicroD outputs a ".Mb" file, consisting of blocks of data that can be loaded into various Dolphinmemories and of addresses associated with particular locations in memories. The memories are asfollows:IM44-bit x 10000-word instruction memory(also contains 60 bits/word of placement and other information)RM20-bit x 400-word register bank memoryIn addition, three other memories called VERSION, IMLOCK, and IMMASK are produced byMicro and consumed by MicroD, but these are invisible to the programmer.There are at present very limited provisions for microcode overlays, as discussed in a later section.3. Error MessagesDuring assembly, error messages and assembly progress messages are output to both the display andthe error file.Micro error messages are in one of two forms, like the following:... source statement ...218...error message-or-... source statement ...ЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuН/О_9sН\О]╣Н/ПFН\О\1Н/Н\ОZґН/Т²ПOТ·Н/ОYLТП@Н\ОWхН/П6Н\ОVDН/П=НxОTН\Н/ПAН\ОR▀Н/П)Н\ОQН/П)Н\ОO┐Н/П-Н\ОMЪН/ Н\ОL{Н/ Н\ОJВН/П/НЇОG╗rТ┤П,Т┬П2НЇОEчТ≤ПCТ≥НЇОDТёП;ТєП'НЇОBIТЁП0ТЄП*НЇО@~ТПGНЇО=Т┐П4Т└П0НЇО;AТдПXТеНЇО9wТ▐Т░ПRНЇО7╛Т┘П9Т├П*НЇО5БТўП!Т╞П;НЇО2pТ≈П4Т≤П-НЇО0╔Т°Т²ПGНЇО.зНxО,sНТП&НО*╦П?НxО)4НП&НЇО%ЕrТҐП1ТЎП#НЇО$ТПHНЇО ╘Т≥П!Т ПDНЇОЁtТ÷НЇОArТ┐П>Т└П#НЇОvТНЇОПAНyОCsНyОБНyОўНyО yЪ пЇ V>Г]╣Dolphin MicroAssemblerEdward R. Fiala9 October 19818TAG+39...error messageThe first example indicates an error on the 218th line of the source file. This form is used forerrors that precede the first label in the file. The second form is used afterwards, indicating anerror on the 39th line after the label "TAG".Note that the line count measures 's in the source, so if you are using Bravo formatting in thesource files, you may have trouble distinguishing 's from line breaks inserted by Bravo'shardcopy command.The "TITLE" statement in each source outputs a message of the form:1...title..IM.address.=.341This message indicates that the assembler has started working on that source file."IM.address.=.341" indicates that the first IM location assembled in this source file is the 341st inthe program. When a number of source files are assembled into a single .Dib file, this messagemay be helpful in correlating source statements with error messages from the postprocessor,MicroD.The most common assembly errors result from references to undefined symbols and from setting asingle instruction field multiple times (e.g., attempting to use the F1 field twice in one instruction).I do not believe that you will have any trouble figuring out what these messages mean, so nocomments are offered here.After Micro has finished an assembly, it returns to the Executive leaving a message like "Time: 22seconds; 0 errors, 0 warnings, 20007 words free" in the system window. Only when the error orwarning counts are non-zero do you have to look in the .Er file for detailed information abouterrors.MicroD errors are discussed in the appendix.4. Debugging MicroprogramsMicroprograms may be debugged directly on the hardware using facilities provided by Midas. Todebug programs you will need to load Midas and its auxiliary files as discussed in the DolphinMidas Manual.Midas facilities consist of actions to boot the Dolphin; load microprograms; set, clear, and examinebreakpoints; start, step, or halt the machine, and examine and modify storage. Addresses definedduring assembly may be examined on the display. Midas contains a command file facility thatallows you to carry out various procedures such as setting up the display and iterating through asequence of diagnostic microprograms.НЇОf╙uТ─Н!цrН4]ТНHYОfЯuНyО_9sНЇО[ЙrТ╠П9Т╡П(НЇОZ Т╠ПcНЇОXUТП-НЇОTЦТ│П+Т┌П8НЇОSТкП8ТлП%НЇОQNТНЇОMэПCНyОKsНЇОGлrТ~ТП7НЇОFТ√П\Т≈НЇОD7Т╛П/ТґП0НЇОBlТТПCТУНЇО@║НЇО=/Т∙П&Т√П8НЇО;eТ▓П@Т⌠П(НЇО9 ТцПYТдНЇО7пТНЇО4^Т■Т∙ПJНЇО2⌠ТїПGТ╗НЇО0хТ╨П"Т╩П<НЇО.ЧНЇО+▄ТП,НЇО&√tТ÷НЇО#$rТ⌡ПSТ° НЇО!YТ╦П.Т╧П0НЇО▐ТНЇОТ░Т▒ПLНЇОRТ║П2Т╒П/НЇО┤Т╪ПNТҐ НЇОҐТ╘П:Т╙П'НЇОРТП%ЪЗЇ╚>ГS`ОDolphin MicroAssemblerEdward R. Fiala9 October 198195. Cross Reference ListingsThe cross-reference program for Dolphin microprograms is a Tenex subsystem called MCross. It iseasier to maintain large programs when cross-reference listings are available, so you may wish tostore your sources on a Tenex directory and make your listings using MCross.Obviously, you can only use MCross if you have a timesharing account on Maxc. If not, you willhave to do without cross-reference listings until MCross is implemented on Alto (no one is workingon that now).A typical dialog with MCross is given below. The program is more-or-less self-documenting andwill give you a list of its commands if you type "?".@MCROSSOutput File:LPT:GACHA8.EPMachine:0(selects Dolphin syntax)Action:U(convert to upper case)Action:N(read def's, no printout)File:D0LANGAction:CL(read def's, produce cross ref)File:Source1Action:CLFile:Source2Action:P(print operation usage statistics)Action:G(print global cross reference)Action:E@6. CommentsMicro ignores all non-printing characters and Bravo trailers. This means that you can freely usespaces, tabs, and carriage returns to format your file for readability without in any way affecting themeaning of the statements.Comments are handled as follows:"*" begins a comment terminated by carriage return."%" begins a comment terminated by the next "%". This is used for multi-line comments.";" terminates a statement. Note that if you omit the ";" terminating a statement, and, forexample, put a "*" to begin a comment, the same statement will be continued on the nextline.Micro's COMCHAR feature provides one method of producing multi-statement conditionalassemblies (This method is now obsolete, replaced by the conditional assembly features discussed inthe next section). COMCHAR is used as follows. Suppose you want to have conditional assembliesbased on whether the microcode is being assembled for a Pilot or Alto-compatible configuration.To do this define "=" as the comment character for Pilot (i.e., COMCHAR[=];) and "#" as thecomment character for Alto-compatible. Then in the source files:*= Alto-compatible configuration only ...statements for Alto-compatible configuration...ЪНЇОf╙uТ─Н!цrН4]ТНHYОfЯuНЇО^оtТ÷НЇО[]rТ█П`НЇОY⌠Т╞П6Т╟П+НЇОWхТПLНЇОTVТ√П%Т≈П:НЇОR▀Т┼Т▀П[НЇОPаТНЇОMOТ╘П1Т╙П-НЇОK└ТП5НyОHцsНyОGbТ─НнНyОFНнН#тТНyОD═НнН#тНyОC@НнН#тНyОAъНн НyО@~НнН#тНyО?НнНyО=╪НнНyО<\НнНyО:ШНнН#тП"НyО9 НнН#тНyО89НнНyО6ыНЇО2tТ÷НЇО.■rТґП>ТўП#НЇО,иТ├ПFТ┤П!НЇО*ЪТНЇО'█НyО$П3НyО!}Т┬П&Т┴П1НyОчТ┘ПFТ├НyОТ┼Т▀ПKНyОIНЇОвТПTНЇОТ┼ПDТ▀НЇОBТ─ПAТ│НЇОwТўТ╞ПKНЇОґТ⌡Т°ПFНЇОБТПAНyО sП%НyО юП3ЪІЇ ²>Г]nDolphin MicroAssemblerEdward R. Fiala9 October 198110*= end of Alto-compatible statements*# Pilot configuration only ...statements for Pilot configuration...*# end of Pilot statementsIn other words, "*" followed by the comment character is approximately equivalent to "%" and isterminated by the carriage return following its next occurrence.7. Conditional AssemblyD0Lang defines IF, UNLESS, ELSEIF, ELSE, and ENDIF macros for doing multi-statementconditional assemblies; IF's may be nested up to four levels deep. The syntax for these is asfollows::IF[Display]; ... statements assembled if Display is non-zero...:ELSEIF[OldDisplay]; ... statements assembled if Display is zero and OldDisplay non-zero...:ELSE; ... statements assembled if both Display and OldDisplay are zero...:ENDIF;Alternatively, UNLESS can be used instead of IF, as follows::UNLESS[Display]; ... statements assembled if Display is zero...:ENDIF;Note that each of the conditional names must be preceded by ":"; the implementation of these isdiscussed in the Micro manual. Any number of ELSEIF's may be used after an IF, followed by anoptional ELSE and a mandatory ENDIF. The arguments to IF and ELSEIF must be integers.Warning: The :IF, :UNLESS, :ELSEIF, :ELSE, and :ENDIF must be the first characters in astatement. In the following example:FlshCore::IF[MappedStorage];... statements ...:ELSE;... statements ...:ENDIF;":IF" is illegal because, due to the "FlshCore" label, ":IF" are not the first characters of astatement.ЪНЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНyО_9sП$НyО]ьНyО\wП)НyО[НЇОWхrТ⌡Т°ПLНЇОUЩТП@НЇОQtТ÷НЇОM∙rТДП(ТЕП+НЇОKкТфПCТгНЇОJНyОG?sНyОEчТП4НyОD}НyОCПHНyОA╪НyО@[ПEНyО>ЗНЇО;╚rП<НyО8ЙsНyО7┴П0НyО6(НЇО2зrТ·ПSТ÷НЇО1Т┤П=Т┬П!НЇО/DТҐП9ТЎНЇО+рwrТ╩П:Т╪НЇО*ТП%НyО'FsНyО%ЕНґО$┘НyО#$НґО!цНyО bНЇОrТБП6ТЦП(НЇОI ЪЮЇ=ГM фDolphin MicroAssemblerEdward R. Fiala9 October 1981118. Simplified Parsing RulesAfter comments, false conditionals, and non-printing characters are stripped out, the rest of the textforms statements.Statements are terminated by ";". You can have as many statements as you want on a text line,and you can spread statements over as many text lines as you want. Statements may be indefinitelylong.However, the size of Micro's statement buffer limits statements to 50010 characters at any one time.If this is exceeded at any time during the assembly of a statement, an error message is output.Since horrendous macro expansions occur during instruction assembly, it is possible that instructionstatements may overflow. If this occurs, the size of the statement buffer can be expanded (Tellme.).The special characters in statements are:"[" and "]"for enclosing builtin, macro, field, memory, and address argument lists;"(" and ")"for causing nested evaluation;"_"as the final character of the token to its left;":"to put the address to its left into the symbol table with value equal to the currentlocation and current memory, and as the first character of a statement to be evaluatedeven in the false arm of a conditional;","separates clauses or arguments;";"separates statements;"#"#1, #2, etc., are the formal parameters inside macro definitions;"01234567"are number components (all arithmetic in octal).All other printing characters are ordinary symbol constituents, so it is perfectly ok to have symbolscontaining "+", "-", "&", etc. which would be syntactically significant in other languages. Also,don't forget that blanks, carriage returns, and tabs are syntactically meaningless (flushed by theprescan), so "T+Q" = "T + Q", each of which is a single symbol.The debugger Midas requires all address symbols to be upper case; since both Micro and MCrosshave switches that convert all source file characters to upper case, you can follow your owncapitalization conventions but must convert to upper case at assembly time using the /U switch.Experience suggests that consistent capitalization conventions are desirable, although there is notmuch agreement on exactly what conventions should be used. In this manual I follow capitalizationconventions which you may consider as a non-binding proposal. My convention is as follows:The first letter of each word is capitalized.When a symbol consists of several words run together, the first letter of each subword iscapitalized (e.g., "NextData," "StkP").When a symbol is formed by running together the first letters from several words, thenthese are all capitalized (e.g., "MNBR,").НЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНЇО^оtТ÷НЇО[]rТ▄ПZТ█НЇОY⌠Тu rНЇОV!Т╔ПEТіНЇОTVТ├ПBТ┤НЇОR▀НЇОOТ▌ПFОN▄sОOrТ▐ НЇОMOТ╩П8Т╪П'НЇОK└Т▐ПDТ░НЇОI╨ТЁТЄПGНЇОGОНЇОD}ТП)НxОA╪sТ─ НнТПEНxО@Т─ НнТНxО>mНнП0НxО<фНнТюП.ТаП&НнО;eТіПFТїНнО:ТП'НxО8]НнНxО6╣НнНxО5НнПAНxО3g НнП0НЇО0rТ■ПBТ∙П#НЇО.MТ╛П*ТґП8НЇО,┐ТдП"ТеП@НЇО*╦ТП?НЇО'FТўuП%Т╞ rНЇО%|ТЮТАП>НЇО#╠Т╣ПTТІ НЇО!ФТгТхuП%rП%НЇО Т└П;Т┘П'НЇОQТгПLТхНxОIТП-НxОAТ═ПYНxОvТП'НxОnТ╞П5Т╟П!НxОєТП*Ъ JЇ]>ГVў%Dolphin MicroAssemblerEdward R. Fiala9 October 198112Micro builtins, memory names, and important assembly directives that should stand out inthe source, such as TITLE, END, IF, etc. are all capitals.Midas also limits address symbols to 13 characters in length; if you assemble longer addresses, youwill still be able to load and run your program with Midas, but you won't be able to examinesymbols longer than 13 characters.Also, avoid using any of the characters "=," "#," "+," "-," and "!" in address symbols; these aresyntactically significant to Midas and may cause trouble when debugging. Finally, avoid definingsymbols that end with the character "@"; the internal symbols in D0Lang.Mc by convention endwith "@," so you might have name conflicts with reserved words if you also define symbols endingwith "@."Statements are divided into clauses separated by commas, which are evaluated right-to-left. Anindefinite number of clauses may appear in a statement.Examples of clauses are:NAME,NAME[ARG1,ARG2,...,ARGN],FOO_FOO1_FOO2_P+Q+1,P+Q+1 is referred to as a "source" while FOO_, FOO1_, andFOO2_ are "destinations" or "sinks".P_STEMP,NAME[N1[N2[ARG]],ARG2]_FOO[X],Further discussion about clause evaluation is postponed until later.9. Statements Controlling AssemblyEach source file should begin with a TITLE statement as follows::TITLE[Source1];The TITLE statement:a.prints a message in the .Er file and on the display which will help you correlatesubsequent error messages with source statements which caused them;b.does a SetTask[0] (discussed later) and resets a number of assembly switches.At the end of a file you may optionally insert an END statement::END[Source1];The END statement prints a message like the title statement's and checks for unterminatedconditionals, but it does not affect the output of the assembler.НЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНxО_rТ▌ПKТ▐НxО]KТП:НЇОYыТ· uТ÷П+rП'НЇОXТ╨Т╩П>НЇОVDТП"НЇОRрТ≥uТ П:r НЇОQТґП8Тўu НЇОO=Т╞Т╟rП5НЇОMrТ┴Т┼ПPНЇОK╗ТНЇОH6Т©ur ТюП2НЇОFkТП7НЇОBЫНxО@7sНxО>░НxО<ИН#тТ╞Т╟П"Н#тО;┬ТП$НxО9АНxО89НЇО4КrПDНЇО/УtТ÷П#НЇО,┐rТП@НyО)аsНЇО&srНxО#Н:ТйП'ТкП*Н:О!6ТПCНxОдН:ПMНЇОRП@НyО▒s НЇОBrТСТТП?НЇОwТПA*Ї0=ГUшшDolphin MicroAssemblerEdward R. Fiala9 October 198113Note that the ":" preceding TITLE and END is optional; inserting the ":" will cause statementevaluation even in the false arm of a conditional, so an appropriate message can be printed to helpdetect :IF's unmatched by :ENDIF's. The "Source1" argument to :END is also optional.You may at any place in the program include an INSERT statement:INSERT[SourceX];This is equivalent to the text of the file SourceX.MC.The message printed on the .Er file by TITLE is most helpful in correlating subsequent errormessages if any INSERT statements occur either before the TITLE statement or at the end of thefile (before the END statement). INSERT works ok anywhere, but it might be harder to figure outwhich statement suffered an error if you deviate from this recommendation.In the event you request a listing by putting "/L" in the Micro command line, the exact stuffprinted is determined by declarations that can be put anywhere in your program.D0Lang selects verbose listing output. However, you will generally not want to print this listing.The MicroD listing is normally more useful during debugging. If you want to modify the defaultlisting control in D0Lang for any reason, you can do this using the LIST statement, as follows:LIST[memory,mode];where the "memory" may be any of the ones given earlier and the mode the OR of the following:20(TAG) nnnnnn nnnnnn (octal value printout in 16-bit units)10alphabetically-ordered list of address symbols 4numerically-ordered list of address symbols 2(TAG) FF_3, JCN_4, etc (list of field stores) 1(TAG) nnnn nnnn nnnn (octal value printout)Note: The listing output will be incorrect in fields affected by forward references (i.e., references toas yet undefined addresses); such fields will be incorrectly listed as containing their default values.Micro has a recently added TRACEMODE builtin which you may prefer to use instead of anassembly listing for the purposes of debugging complicated macros. TRACEMODE allows symboltable insertions and macro expansions to be printed in the .Er file. See the Micro manual fordetails about TRACEMODE.10. Forward ReferencesMicro and D0Lang have an extremely limited ability to handle forward references. The only legalforward references are to instruction labels from branch clauses. Anything else must be definedbefore it is referenced.ЪНЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНЇО_rТІП@ТЇНЇО]KТ▌П#Т▐П@НЇО[─ТПUНЇОXП@НyОUMsНЇОQЧrП6НЇОN▄ТкП&ТлП6НЇОLбТ⌡П?Т°НЇОJВТ┤П\Т┬НЇОI-ТПJНЇОE╩Т©ТюПMНЇОCПТПOНЇО@~Т╗П'Т╘urНЇО>ЁТ⌡П#Т°П<НЇО<ИТЇПSТ╦НyО:'sНЇО6ыrТ▒ПNТ▓НyО4sНТП:НyО2ІНП.НyО1UТ─НТНyО/УТ─НТП(НyО.■Т─НТП&НЇО+EurТ┘ПdНЇО){Т П<Т⌡П+НЇО& ТфПDТгНЇО$>Т■Т∙ПKНЇО"sТЎП^НЇО ╘ТНЇОЁtТ÷НЇОArТ⌡urП&Т°НЇОvТ╡ТЁПGНЇО╛Т LЇe>ГSіШDolphin MicroAssemblerEdward R. Fiala9 October 19811411. IntegersMicro provides builtin operations for manipulating 20-bit assembly-time integers. These havenothing to do with code generation or storage for any memories. Integers are used to implementassembly switches and to control Repeat statements. The operations are given in the table belowand there is some additional discussion in the Micro Manual:Set[NAME,OCT]Defines NAME as an integer with value OCT. Changes the value of NAME ifalready defined.Select[i,C0,...,Cn]i is an integer 0 to n. Evaluates C0 if i = 0, C1 if i = 1, etc.Add[O1,...,O8]Sum of up to 8 integers O1 ... O8.Sub[O1, ... ,O8]O1-O2-...-O8IFE[O1,O2,C1,C2]Evaluates clause C1 if O1 equals O2, else C2.IFG[O1,O2,C1,C2]Evaluates C1 if O1 greater than O2, else C2.Not[O1]Ones complement of O1.Or[O1,O2,...,O8]Inclusive 'OR' of up to 8 integers.Xor[O1,O2,...,O8]Exclusive 'OR' of up to 8 integers.And[O1,O2,...,O8]'AND' of up to 8 integers.LShift[O1,N]O1 lshift NRShift[O1,N]O1 rshift NOCT in the Set[NAME,OCT] clause, may be any expression which evaluates to an integer, e.g.:Set[NAME, Add[Not[X], And[Y,Z,3], W]]where W, X, Y, and Z are integers.If you want to do arithmetic on an address, then it must be converted to an integer using the IPoperator, e.g.:IP[FOO]takes the integer part of the address FOOAdd[3,IP[FOO]]is legalAdd[3,FOO]is illegalSome restrictions on doing arithmetic on IM addresses are discussed later.12. Repeat StatementsThe assortment of macros and junk in the D0Lang file successfully conceals Micro's complicatedmacro, neutral, memory, field, and address stuff for ordinary use of the assembler.However, using the Repeat builtin may require you to understand underlying machinery--in adiagnostic you might want to assemble a large block of instructions differing only a little bit fromeach other, and you want to avoid typing the same instruction over and over.Instruction statements are assembled relative to a location counter called ".". Originally set to 0 ,"." is incremented by one every time an instruction is assembled. To do a Repeat, you mustdirectly reference "." as follows:Repeat[20, . [(instruction statement)]];НЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНЇО^оtТ÷НЇО[]rТАП2ТБП+НЇОY⌠Т═П-Т║П2НЇОWхТєП'Т╔П9НЇОUЩТП<НxОSНПТП-НxОI√НПП,НxОGОНПНxОFHНПП#НxОD═НПП#НxОBЫНПНxОARНП НxО?╙НП НЇО<\rТ╦ Т╧ПQНxО9 sТП%НЇО6KrП"НЇО2зТ╒ТёПZНЇО1ТНyО.MsНПП)НyО,М НПНyО+▄ НП НЇО(=rПJНЇО#GtТ÷НЇОуrТ╟П4Т╠П*НЇОТПSНЇО≥ТвТьПAНЇОнТ²П_Т·НЇОТПLНЇО▒Т·П;Т÷П+НЇОгТеТфПBНЇОЭТП"НyО ;sП(Ъ├Ї =ГZС Dolphin MicroAssemblerEdward R. Fiala9 October 198115This would assemble the instruction 20 times. If you want to be bumping some field in theinstruction each time, you would proceed as follows:Set[X,0];Repeat[20, . [(Set[X,Add[X,1]], instruction statement)]];where the instruction statement would use X someplace.For a complicated Repeat, you may have to know details in D0Lang. For this you will have todelve into it and figure out how things work.13. ParametersParameters are special assembly-time data objects that you may define as building blocks fromwhich constants, RM, or IM data may be constructed. Three macros define parameters:MP[NAME,OCT];makes a parameter of NAME with value OCTSP[NAME,P1,...,P8];makes NAME a parameter equal to the sum of P1,...,P8, which are parameters orintegers.NSP[NAME,P1,...,P8];makes NAME a parameter equal to the ones complement of the sum of P1,...,P8,which are parameters or integers.The parameter "NAME" is defined by the integer "NAME!" (The "!" is a symbol constituentadded so that a constant, small constant, or RM address can have an identical NAME.), so it ok touse the NAME again as an address or constant. However, you cannot use it for more than one ofthese.14. ConstantsThe hardware allows a constant to be generated on B that is the 10-bit FF field of the instruction ineither the left or right half of the 20-bit data path with 0 in the other 10-bit byte."Literal" constants such as "322C" or "32400C" may be inserted in instructions without previousdefinition.Negative constants such as "-400C", "-32400C", etc. are also legal.Left-half-word and right-half-word constants may be constructed from integers by applying,respectively, the HiA and LoA operators to a 20-bit integer. An optional second argument to HiAshould be an integer in the range 0 to 17; if provided, this argument is or'ed with bits 0:3 of thefirst to produce the task number and high four address bits for APCTask&APC _. An exampleusing HiA and LoA is as follows:RTemp _ HiA[DispStartLoc,DispTask];*Bits 0:7 (DispTask in 0:3)RTemp _ (RTemp) or (LoA[DispStartLoc]);*Bits 10:17НЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНЇО_rТнП#ТоП7НЇО]KТП4НyОZ┼sНyОY)П9НЇОUзrП6НЇОRhТ╚ПAТ╛НЇОP·ТП-НЇОK╗tТ÷НЇОH6rТиП$ТйП9НЇОFkТПTНxОC╘sНПП(НxОAъНПТ┘П*Т├П#НПО@~НxО>ЁНППLНПО=SТП!НЇО:rТгП;ТхНЇО89Т▐Т░ПBНЇО6oТ▒Т▓ПWНЇО4єНЇО/ўtТ÷ НЇО,Т╞П+Т╟П5НЇОIsТП1НxОF╡s НxОEQНxОCПНxОB▐ НxОA.НЇО=ЮrТгПZТхНЇО<ТПUНxО9Ts НПП'НxО7┴НПП5НЇО2ІtТ÷НЇО/DrТ┐П%Т└П>НЇО-zТбПFТцНЇО+╞Т╗Т╘ПEНЇО)Д НЇО&sТП'НyО#╠s НнНЇО brТ▒ПOТ▓НЇО≤ТНyОжsНЇО┤rП0НЇОТ═Т║ПRНЇОKТП:ЪЧЇ=ГUФDolphin MicroAssemblerEdward R. Fiala9 October 198117Note: The TITLE statement at the beginning of a file does a SetTask[0].ЪНЇОf╙uТ─Н!цrН4]ТНG╘ОfЯuНЇО_rПC~Ї^о2з <!Dolphin MicroAssemblerEdward R. Fiala9 October 19811816. Assembling Data for RMRM addresses are allocated by RV statements in one of the following ways:RV[name, disp, P1, P2, ... , P7];RV[name, , P1, P2, ... , P7];RV[name, disp];RV[name];RV[name, , value];RV2[name0, name1, disp0];RV4[name0, name1, name2, name3, disp0];The first argument of RV is the "name" of the RM address to which you will subsequently refer ininstructions.The second argument "disp" is a displacement between 0 and 77. This specifies the low six bits ofthe RM address. The top two bits are determined by the top two bits of the task number, declaredby the last SetTask statement. If "disp" is omitted, the RM address is allocated at the last locationplus 1.The remaining 7 arguments are parameters or integers summed to determine the value loaded intothat location. If all of these are omitted, then the location will be uninitialized.RV2 and RV4 macros allow definition, respectively, of two consecutive or four consecutive RMlocations. The first two (four) arguments are the names of the consecutive registers, and the finalargument is the displacement of the first named register (0 to 77); no provision is made forassembling values into registers defined this way. It is convenient to define registers with RV2/4rather than one-at-a-time, when they are constrained to be consecutive by some usage. Forexample, target registers for PFetch2/4 should be defined by RV2/4.Avoid assigning useless initial values to variables because this will prevent the "Compare" functionin Midas (which compares the microstore image against what you loaded) from reporting fictitiouserrors. In a system microprogram (as opposed to a diagnostic), any occurrence of a variable with aninitial value is probably a programming error since it requires reloading the microcode to restore theinitial value. Hence, you probably should initialize such registers with your program.Also, boot microcode does not allow any memories except IM to be initialized from the boot EPROM, andcurrent software for loading microcode overlays is also limited to IM. For these reasons the usual practice isto put code for initializing RM into a "throwaway" page which can be overwritten by something else after itis executed.The hardware imposes a number of strange constraints upon RM placement. For example,addresses used as base registers must (usually) be even, addresses for PFetch4/PStore4 must(usually) be origined 0 mod 4, and addresses for PFetch2/PStore2 must (usually) be at evenlocations (exception: stack double-words). Also, RM is partitioned so that only locations 0 to 77 areaccessible to tasks 0 to 3, 100 to 177 to tasks 4 to 7, 200 to 277 to tasks 10 to 13, and 300 to 377 totasks 14 to 17. Tasks 1 to 3 in each group of 4 are further limited because the task number isOR'ed into high address bits in various ways. These constraints will be a source of many programbugs.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷НЇО[]qТПIНxОX°sП!НxОVТНxОUMНxОSіНxОQЧНxОPWНxОN╟П'НЇОKaqТ┬П)Т┴П7НЇОI√НЇОF$Т█П:Т▌П(НЇОDZТ┤Т┬ПMНЇОB▐Т▌Т▐ПGНЇО@еТНЇО=SТ√П;Т≈П#НЇО;┬ТПUНЇО8ТҐПYТЎНЇО6KТ²Т·ПOНЇО4│ТыП/ТзП-НЇО2ІТ╔П9ТіП*НЇО0ЛТЕТФП@НЇО/!ТПCНЇО+╞Т∙ПEТ√НЇО)ДТ°ПUТ² НЇО(Т┌П?Т┐П%НЇО&OТ─П'Т│П?НЇО$┘ТПWНyО!YsТ ПeНyОЬТ█ПGТ▌П(НyО≤Т▐ПDТ░П'НyО7ТНЇОХqТНПGТО НЇОТПП%ТЯП6НЇОSТЮПEТАНЇО┬Т┐ПfНЇОЎТ┴П&Т┼ПAНЇОСТ╞ПDТ╟НЇО)Т▓П-Т⌠П4НЇО ^ЪzЇ =ГZТDolphin MicroAssemblerEdward R. Fiala9 October 198119You must be careful to assign a "disp" that satisfies all the uses of each RM address. If you screwup, the assembler will indicate an error when you illegally reference the RM location in aninstruction.Note: Suppose that you want tasks 10, 11, 12, and 13 to share a section of microcode but useindependent RM locations. Then you do a SetTask[10] before that section of the program, and youallocate a block of RM locations in the range 100-117 and refer to these locations in the program;you also allocate parallel blocks of RM locations in the ranges 120-137, 140-157, and 160-177 foruse by tasks 11, 12, and 13, respectively. In this way, the program will do what you want. If thefour tasks have some other RM locations that are shared, allocate these in the range 160-177, so thatthey will be accessible to all four tasks.Sometimes you may want to use several different names to refer to the same RM location. To dothis, define the first name with RV, as above; you can then define synonyms in several ways, one ofwhich is as follows:RM[FOO1, IP[FOO]];This defines the address FOO1 at the same location as the (previously-defined) address FOO.17. Assembling Data Items In the Instruction MemoryIf you do not want to clutter RM with infrequently referenced constants or variables, and if you arewilling to cope with the hardware kludges for reading/writing the instruction memory as data, thenyou can store data items in IM.To assemble a table of data in the instruction memory:Set[T1Loc,100];IMData[(TABLE1: LH[P1, ... , P8] RH[P1, ... , P8], At[T1Loc])];IMData[(LH[P1, ... , P8] RH[P1, ... , P8], At[T1Loc,1])];...where TABLE1 is an IM address symbol equal to the location of the first instruction in the table,P1, ..., P8 are parameters or integers. LH stores the sum of up to 8 parameters in the left-half ofthe IM word and RH, in the right-half; these macros do not allow you to specify the remainingfour bits of the 44-bit instruction--the assembler will ensure that the data has valid parity by storinga 0 or 1 in the low-order bit of the RX@ field (which is one of the four bits you cannot specify)."At" is discused in the "Placement" section later.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТ▄П5Т█П/НЇО]KТЦП"ТДП9НЇО[─НЇОXpqТІП)ТЇП/НЇОVDТ┤ПXТ┬НЇОTyТ≈Т≤ПBНЇОR╞Т╘ПaНЇОPДТ≈Т≤ПGНЇОOТ│Т┌ПHНЇОMOТП*НЇОIщТ∙П>Т√НЇОHТ┐П`Т└НЇОFHТНxОC├sНЇО@7qТтТуПKНЇО;ArТ÷П4НЇО7пqТ└Т┘П^НЇО6Т░ПWТ▒ НЇО4:ТНЇО0хП6НxО.sНxО,іП?НxО+EП9НxО)ДНЇО&√qТ°ПGТ²НЇО$кТ П=Т⌡П'НЇО#ТґП]НЇО!6Т┬ПCТ┴П%НЇОkТ≈ПMТ≤НЇО║ТП2╛ЇZ>ГJ╠шDolphin MicroAssemblerEdward R. Fiala9 October 19812018. General Comments on Instruction StatementsThe general forms of an instruction statement are as follows:TAG:branch clause, T_rmaddr_(A phrase) and (B phrase), function, placement;TAG:branch clause, T_A phrase, B phrase, function, placement;TAG:branch clause, A phrase, RMAddr_B phrase, function, placement;-or-TAG:branch clause, PFetch1[rbase, rdest, f2], placement;TAG:branch clause, PFetch1[rbase, rdest], f2, placement;where the first three examples are "regular" instructions and the last two, "memory reference"instructions.Rule: TAG is an optional IM address symbol or label; it must appear first in the instructionstatement.TAG may be referenced from branch clauses in other instructions, as discussed in the "Branching"section, and it will appear in the output file for use in debugging.Rule: Clause order is totally arbitrary; it doesn't matter which ones appear first in the statement.However, you might wish to follow a consistent ordering convention for program readability.Placement clauses, A phrases, B phrases, ALU clauses, and memory reference clauses are discussedin separate sections and only outlined here.The ALU operation in the first example is a function of both H1 and H2; it involves only H1 inthe second, and only H2 in the third. In this manual, the H1 and H2 data paths are referred to as"A" and "B," respectively, and the output of the ALU, loaded into H3P, is referred to as "LU."Rule: In an ALU operation involving both A and B, the A phrase must appear to the left of the Bphrase.Rule: An F1 or F2 function that either sources or sinks A will appear in the A phrase; one thateither sources or sinks B will appear in the B phrase; one that involves neither A nor B will appearas a separate clause in the instruction.Data-routing clauses have one or more "_"'s in them and require parentheses in some places tocause evaluation in the correct order. One of these clauses is evaluated from right-to-left, or from"sources" to "sinks."If there is only one source and one sink in the clause, no problem: simply write "sink_source",e.g.:T_RMAddr,The assembler figures out how to route data from the RM addressRMAddr onto A, through the ALU, and into T.RMAddr_34C,Again the assembler figures out how to construct the constant 34, route itonto B, through the ALU, and into the RM address RMAddr.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷П/НЇО[]qТП=НyОX°sН(ПGНyОW;Н(П9НyОUзН(П>НґОTyНyОSН(П4НyОQ╦Н(П4НЇОNiqТйП"ТкП<НЇОL·НЇОI-tqТеПHТфНЇОGb НЇОCПТ■ПTТ∙НЇОB%ТПDНЇО>ЁtqТ═Т║ПGНЇО<ИТДТЕПAНЇО9wТ∙П@Т√НЇО7╛ТП,НЇО4:Т·Т÷П@НЇО2pТ█П)Т▌П9НЇО0╔ТїПIТ╗НЇО-3tqТ┬П[НЇО+iНЇО'ВtqТ÷ПAТ═НЇО&,Т┼П]Т▀НЇО$aТП(НЇО ОТ╟ПKТ╠НЇО%Т≥ПeНЇОZТНЇОХТіП#ТїП=НЇОНxО\sН!ТяП4Тр Н!ОШТП+НxОT Н!Т─П4Т│Н!ОСТП8Ъ NЇп>ГW;Dolphin MicroAssemblerEdward R. Fiala9 October 198121When you have A or B phrases embedded in ALU expressions, then you have to use parentheses,e.g.:T_(StkP_RMAddr)+1,The assembler routes RMAddr onto A, loads StkP from A with an F2function, selects the A+1 ALU operation, and sets the LT bit in theinstruction so that T will be loaded from the ALU.T_(LoadTimer[RMAddr])+(SALUF_T)The assembler routes RMAddr onto A, selects the LoadTimer function inF1, routes T onto B, selects the SALUF_ function in F2, selects the"A+B" ALU operation, and sets the LT bit to load T from the ALUoutput.In assembling the first clause above, the assembler proceeds in the following way:a.RMAddr is looked up first and recognized as an RM address. Error checks ensurethat RMAddr can legitimately be referenced by the current task. If so, the propervalue is assembled for the RSel, RMod, RX, and MemIns fields of the instruction.The assembler's macros leave a neutral symbol "RB" at the end of this evaluation tocheck for routing errors later.b."StkP_" is looked up next; this macro expands to store the correct code in the F2field of the instruction and leaves a neutral symbol "A_" to check for routing errors.c."A_RB" is looked up; because routing RB onto A is legal, this "connection macro" isdefined and expands to leave the neutral "A." (If the routing had been illegal, thenMicro would have printed an error message like "A_RB undefined.")d."A+1" is looked up; this macro expands to store the correct code in the ALUFinstruction field and leaves behind the neutral symbol "LU" to check for routingerrors.e.Then "T_" is looked up; it is a macro that expands to store a 1 into the LT field ofthe instruction, leaving the neutral "LU_."f.Finally, "LU_LU" is looked up; it is a "connection" macro that does nothing andleaves behind the neutral "LU"; since there is no more text in the clause this finalneutral is thrown away.Note: The "()" in the first example above are not optional. If you omit them, the assembler wouldlook up "RMAddr+1", which would be undefined.One general idea in the above is that at each stage the source is routed only as far as necessary toload it into the destination.Note:T_StkP_RMAddr,is legalT_StkP_(RMAddr),is legalT_(StkP_RMAddr),is legalStkP_T_RMAddr,is illegalНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТ≤ПBТ≥НЇО]KНxОZ┼sН!Т║Т╒П3Н!ОY)Т╡ТЁП&Н!ОWхТП2НxОV!Н!ОTюТ┐Т└П8Н!ОS_ТІТЇП#Н!ОQЧТёП+ТєН!ОP·НЇОMOqТПRНxОIщН:Т╘Т╙П<Н:ОHТ╡П9ТЁН:ОFHТЄП5Т╣Н:ОD}Т ПSН:ОB╡ТНxО?AН:ТўП-Т╞П$Н:О=vТ⌠Т■П>НxО:Н:Т├П1Т┤П"Н:О89Т⌡П-Т°П(Н:О6oТПAНxО2ЩН:ТйТкП4Н:О12ТмП;ТнН:О/hНxО+ЖН:Т■Т∙П=Н:О*+ТП+НxО&╧Н:Т╣ТІП?Н:О$НТґТўП;Н:О#$ТНЇО╡pqТ┐Т└П?НЇОГТП-НЇОuТ∙Т√ПQНЇО╚ТНxОИuН⌡s Н!Н⌡О┬Н!Н⌡О(Н!Н⌡Ог Н! ЪЙЇє=ГVgDolphin MicroAssemblerEdward R. Fiala9 October 198122The last clause above is illegal because, by the time the assembler recognizes StkP_, it has alreadyrouted the source data past A and through the ALU, and there is no path from the ALU to StkP.The assembler is not clever enough to remember that the data originally started on A.Here are some more "()" examples:T_(RMAddr)+T,is legal--"()" are required around RM addresses in combination withother stuff.T_RMAddr,is legal--"()" optional around an RM address all by itselfT_(RMAddr)+(T),is legal--"()" optional around "T."T_((RMAddr)+T),is legal--extra "()" around an entire source always OK(T_(RMAddr)+T),is legalT_T+(RMAddr),is illegal--you cannot reverse the A and B phrases.RMAddr_(RMAddr)+(2C)is legal--"()" required around constants in combination with other stuff.The last two examples at the beginning of this section show the form of "memory reference"instructions. In the first example, the F2 field is used instead of T to specify the displacement forthe reference; in the second example, T is used as the displacement so F2 is available to specifysome function. Memory reference clauses are discussed later.19. RM and STK PhrasesThe hardware complicates RM references by providing only six bits of RM address in theinstruction. The remaining two address bits come from the task number. The programmer mustdeclare the task number with SetTask before any references.RM addresses can source A and can be used in ALU phrases. In this case, the RM address has tobe enclosed in "()."RM addresses can be used as sinks for ALU operations and ALU sources (which the assemblerroutes through the ALU). For these simply write the register name followed by "_".Some examples of clauses involving RM are as follows:RMAddr_(RMAddr)+TUse in an ALU expression and as a sink.RMAddr_TThe assembler automatically routes T through the ALU and intoRMAddr.PCF[RMAddr]_PCF[RMAddr]You really mean RMAddr_PCF[RMAddr], but due to the vagaries ofthe assembler you write it this way.T_(PCF[RMAddr])+TUse with cycler-masker operation PCF.T_PCF[RMAddr]+T"()" not mandatory with these.T_RMAddr"()" optional when RMAddr not combined with other text.DB_RMAddrUse with an A sink.T_(SB_RMAddr)+TUse with an A sink inside an ALU operation.The assembler will detect all illegal RM references. In other words, if the RM word isunaddressable by the currently selected task, or if it is required to be even or quadaligned, theassembler will check for this and indicate any error.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТ∙П0Т√П4НЇО]KТ≈П]НЇО[─ТПUНЇОXП!НxОUMsН!ТмПCН!ОSЛТНxОREН!П:НxОP·Н!П#НxОNЖН!П6НxОMOН!НxОK╗Н!П3НxОJН!ТєП<Т╔НЇОF╡qТоПGТпНЇОDГТ■Т∙ПQНЇОCТ╚ПVТ╛ НЇОARТП=НЇО<\rТ÷НЇО8ЙqТЖПDТВНЇО7ТєП\НЇО5UТП;НЇО1ЦТ█П$Т▌П:НЇО0ТНЇО,іТІПDТЇНЇО*шТПSНЇО'iП5НxО$╗sН!П'НxО#Н!ТП,ТН!О!═НxОЬН!Т╦П;Т╧Н!О≤ТП$НxОПН!П%НxОIН!НxО╒Н!П7НxОЗН!НxОSН!П+НЇОqТПHТНЇО:Т╩ПEТ╪НЇОoТП5 нЇ(>ГXЦDolphin MicroAssemblerEdward R. Fiala9 October 198123References to the stack always read the word pointed to by StkP, then adjust the stack pointer inthe ways discussed in the "A Phrases" section; if the stack is written, the modified address is usedfor the write. The various Stack terms may be used interchangeably with RM addresses where theyare legal. Also note the following:Stack&+1_(Stack&+1)+Tis legal.Stack&+1_(Stack)+Tis illegal.The last example is illegal because you must use the same StkP modifier in both read and writeparts of the instruction.Occasionally you may wish to create a constant whose value is an RM address. To do this you canuse the following kludge:B_IP[RMAddr]CThis puts a constant whose value is the address of RMAddr onto B.20. Cycler-Masker PhrasesThe semantic cycler-masker operations, operating on RM data, are as follows:LSh[RA, n]Left shift the RM address RA n positions (n = 1 to 17).RSh[RA, n]Right shift RA n positions (n = 1 to 17).LdF[RA, pos, size]Right-justify or load an arbitrary field from RA; POS is the left bit of the field andSIZE is the number of bits in the field.RCy[RA, n]Right cycle RA n positions (n = 1 to 17).LCy[RA, n]Left cycle RA n positions (n = 1 to 17).Dispatch[RA, pos, size]Loads APC with any field of size less than 4 bits from RA; the following instructionmust contain a Disp control clause to carry out the dispatch to the location atPage[0:3],,JA[0:3],,APC[14:17].RHMask[RA]= RA & 377.LHMask[RA]= RA & 177400.Zero= 0.FixVA[RA]= RSh[RA,1] & 40100.Formn[RA]= RA & n (n = 0 to 10).Form-n[RA]= RA & -n (n = 2 to 10).Nib0Rsh8[RA]= RSh[RA,10] & 360, which is the first 4-bit nibble in RA right-shifted 10.For these operations, the assembler fabricates values for F1, F2, and BSel to cause the appropriateshift and mask. RA may be any normal RM address or one of the special ones that have RMod=1and don't use F1 or F2 in their specification.In addition to the cycler-masker phrases discussed here, the various forms of the NextData andNextInst functions discussed later use the cycler-masker to extract either the left or right byte fromthe selected RM word.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТ═ПVТ║ НЇО]KТ≤П>Т≥П&НЇО[─Т┤ПUТ┬ НЇОYІТП$НxОVТsН!НxОUMН! НЇОQЧqТ╚Т╛ПCНЇОP4ТНЇОLбТ┼П%Т▀П;НЇОJВТНxОH6sНЇОDГqПAНЇО?ЯrТ÷НЇО<qТПLНxО9ҐsТ─ Н░ТП3НxО7СТ─ Н░ТП$НxО6(Т─Н░ТўТ╞ПAН░О4гТП(НxО2ЩТ─ Н░ТП$НxО12Т─ Н░ТП$НxО/hТ─Н░Т╛ТґПKН░О.ТО ТППAН░О,іНxО*ш Н░Т НxО) Н░ НxО'FН░НxО%|Н░НxО#╠Н░НxО!Ф Н░НxО Н░ПKНЇОмqТ√П.Т≈П5НЇОТ┌П%Т┐П7НЇО8ТП.НЇОфТ╪П2ТҐП,НЇОШТ▓ПfНЇО1ТЪPЇЙ=ГV!Dolphin MicroAssemblerEdward R. Fiala9 October 19812421. A PhrasesAll of the A sources use the RMod and RSel instruction fields; some also use the F1 and F2 fieldsin conjunction with these. An A source can be any of the following:ADummy source for clause splitting. It indicates that the source for some sink is ALUA(You should never need to use this because normally the ALUA sink and source are writtentogether separated by "_" or the ALUA source is embedded in the ALU phrase.).RAddrAn RM address.StackRM addressed by StkPStack&-nRM addressed by StkP; StkP_StkP-n (n = 1, 2, or 3) after the read (and before the write,if any).Stack&+nRM addressed by StkP; StkP_StkP+n (n = 1, 2, or 3) after the read (and before the write,if any).PCF[RAddr]RAddr must be quadaligned--i.e., its low two address bits must be 0.SB[RAddr]RAdr must be quadaligned.DB[RAddr]RAdr must be quadaligned.NextInst[RAddr]Instruction dispatch; incorporates both the NextInst F1 function and the PCF[RAddr] cyclermasker operation, so RAddr must be quadaligned. See the "NextData and NextInst"section.CNextInst[RAddr]Like NextInst; see the "NextData and NextInst" section.NextData[RAddr]Incorporates both the NextData F1 function and the PCF[RAddr] cycler masker operation,so RAddr must be quadaligned; see the "NextData and NextInst" section.CNextData[RAddr]Like NextData; see the "NextData and NextInst" section.BBFA[RAddr]Also a dispatch (no special restrictions on RAddr); uses F1 and F2.BBFB[RAddr]Uses F1.WFA[RAddr]Uses F1.WFB[RAddr]Uses F1.RF[RAddr]Uses F1.BBFX[RAddr]Uses F1.The A sources below use RMod and RSel to specify external R-bus sources and use the cycler-masker to extractindividual registers from multi-field sources.GetRSpec[n]Used to place a multi-field word on A. n is a 7-bit value whose leading bit is placed inRMOD and next 6 bits in RSEL. You should normally prefer to use one of the explicitmacros given below instead of GetRSpec[n].SStkP&NStkP= GetRSpec[103] SStkPSaved StkP; uses F1 and F2. NStkPStkP (ones comlemented); uses F1 and F2.ALUResult&NSALUF ALUResultUses F1 and F2. NSALUFUses F1 and F2.MemSyndromeMemErrorCycle&PCXF= GetRSpec[127] CycleControlUses F1 and F2 (= DBXReg..MWXReg) DBXRegUses F1 and F2. MWXRegUses F1 and F2. PCXRegUses F1 and F2 PCFRegUses F1 and F2.PrinterUses F2.Timer= GetRSpec[133]НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷ НЇО[]qТ▄ПCТ█НЇОY⌠ТПDНxОVяsН/Т╞П9Т╟Н/ОUpТ┐Т└ПBН/ОTТФП;ТГНxОRhН/Т НxОPаН/НxОOН/Т▀Т▄ПCН/ОM╧ТНxОLН/Т─Т│ПLН/ОJ╠ТНxОH Н/ПDНxОFkН/НxОDдН/НxОCН/Т▐П7Т░П#Н/ОA╪ТяП4ТрН/О@[НxО>ЁН/ТП7НxО=Н/Т═П=Т║Н/О;╚ТПFНxО:Н/П7НxО7f Н/ПCНxО5Ў Н/НxО4 Н/НxО2p Н/НxО0хН/НxО/! Н/НxО,┐Т⌡Т°ПPНxО+"ТП.НxО(└ Н/Т Т⌡ПJН/О'#Т°ПTН/О%бТП*НxО$ Н/НxО"sТ─Н/ТНxО лТ─Н/ТП$НxО%НxО}Т─ Н/Т НxОжТ─Н/Т НxО/ НxО┤НxОЮ Н/НxО9Т─ Н/ТНxО▒Т─ Н/Т НxОЙТ─ Н/Т НxОCТ─Н/Т НxО⌡Т─Н/Т НxОТН/НxОMН/ Ї*=Г\АiDolphin MicroAssemblerEdward R. Fiala9 October 198125DBSBUses F2.RS232MNBRUses F2.APCTask&APC= GetRSpec[143] APCTaskUses F1 and F2. APCUses F1 and F2.APC&APCTask= GetRSpec[143] (synonym)CTask&NCIA CTaskUses F1 and F2. NCIAUses F1 and F2 (= CIA ones complemented).CSDataPage&Par&Boot= GetRSpec[157] PageUses F1 and F2. ParityUses F1 and F2. BootReasonUses F1 and F2.Rule: Those of the above sources that accept a normal RM address as an argument, namelyPCF[RA], SB[RA], DB[RA], WFA[RA], BBFB[RA], WFB[RA], RF[RA], and BBFBX[RA], requirethat this same form be used when writing RA in the same instruction; i.e.:PCF[RMAddr]_(PCF[RMAddr])+Tis legalRMAddr_(PCF[RMaddr])+Tis illegalThis unfortunate kludge is required because PCF[RMAddr] will set RMOD to 1, while RMAddr_will set RMOD to 0, causing an assembly error.Sinks for A are the ALU and a number of other registers selected by functions. A sinks can be anyof the following:any ALU expression or ALU sink (T_, RAddr_, or LU_)A_No-op sink--simply routes the selected A source onto ALUA.APCTask&APC_Uses F1 and F2Restore_Uses F1 and F2StkP_Uses F2CycleControl_Uses F2SB_Uses F2DB_Uses F2MNBR_Uses F1 and F2PCF_Uses F1 and F2Printer_Uses F221. B PhrasesB sources can be any of the following:BDummy source for clause splittingConstantsUses FF--see earlier constant sectionTНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНxО_9sН/НxО]▓НxО[ЙН/НxОZC Н/НxОX°Т─Н/Т НxОVТТ─Н/Т НxОUM Н/НxОSі НxОQЧТ─Н/Т НxОPWТ─Н/ТП%НxОN╟НxОMН/НxОKaТ─Н/Т НxОI╨Т─Н/Т НxОHТ─Н/Т НЇОDдtqТнТоП?НЇОBЫТ╘ПKТ╙НЇОA.ТПJНyО>sН&∙НyО<╒Н&∙ НЇО9TqТ≤П+Т≥П.НЇО7┴ТП.НЇО4Т┐ПQТ└НЇО2LТНxО/▀sП3НxО-ДН/П:НxО,<Н/ НxО*∙Н/ НxО(НН/НxО'FН/НxО%÷Н/НxО#ЬН/НxО"PН/ НxО ╘Н/ НxОН/НЇО/rТ÷ НЇОҐqТП&НxОШsН~П!НxОTН~П%НxОґЪ2Ї┼=ГW│Dolphin MicroAssemblerEdward R. Fiala9 October 198126B sinks can be any of the following:B_No-op destination--simply routes source onto B.RS232_Uses F1SALUF_Uses both F1 and F2.CTD_Uses both F1 and F2.any ALU expression or ALU sink23. ALU ClausesIn the ALU operations given below, the "A" and "B" components may be any A and B phrases,respectively:BAA and BA or BA xor BA#BA and not BA or not BA xnor BA=BA+1A+BA+B+1A-1A-BA-B-1A SALUFOP BRule: For all ALU operations except the "A" and "B" operations, the A phrase must always beenclosed in "()"; the B phrase must be enclosed in parentheses unless it is T; "()" are optionalaround T.You must not, for example, write "A and not B" as "A and (not B)"; in other words, it is illegal toput random "()" in the name of the ALU expression, even though that may clarify the meaning. Ifyou tried to do this, the assembler would fail to recognize "not B" and flag an error. The "()" areonly legal around the "A" and "B" parts of the ALU phrase.The arithmetic operations, "A-1," "A+1," "A+B," "A+B+1," "A-B," and "A-B-1" may optionallybe accompanied by the standalone clause "UseCOutAsCIn," which causes the ALU carry-in to bethe carry-out of the last ALU operation for the same task. The value of the carry-out may befrozen across instructions by means of the FreezeResult standalone function."UseCOutAsCIn" cannot be used with the "A" operation because the logical rather than the arithmetic formof the "A" operation is used by the hardware.Legal sinks for ALU phrases are:RAddr_Any RM addressНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qП$НxО\TsН~П/НxОZґН~НxОYН~НxОW^Н~НxОUЇНЇОPДrТ÷НЇОMrqТ╒П"ТёП7НЇОK╗НyОHФsНyОG┘НyОF$ТНyОDдНyОCcТ─Н░НyОBТ НyО@║ НyО?AТ─Н░НyО=ЮНyО<НyО;НyО9ҐНyО8]НyО6ЭНyО5⌡Т НЇО2LtqТіТїП?НЇО0┌ТЇП>Т╦П"НЇО.ЇТНЇО+EТ┴П4Т┼П/НЇО){Т┤П>Т┬П"НЇО'╟Т▐ПLТ░НЇО%ЕТП:НЇО"sТ┌П8Т┐П"НЇО ╘Т║ПUТ╒НЇОчТ╦Т╧ПMНЇОТПLНyОRsТ■ПHТ∙НyОЯТП-НЇОёqНxОАsН! ЇЎ=ГUMТDolphin MicroAssemblerEdward R. Fiala9 October 198127Stack_Stack sinksStack&+n_Stack&-n_T_LU_This null sink is necessary when the ALU operation must be "A" or "B"for a subsequent branch condition or to interlock/not interlock an RMreference, even though no real destination is being loaded with the ALUoutput.Here are some examples of ALU clauses:T_(RAddr)+T"()" optional around T, mandatory around RAddr.T_RAddr"()" optional around RAddr uncombined.T_(RAddr)also ok.RAddr_(RAddr) xor (377C)"()" mandatory.RAddr_T_377C"()" optional when constant uncombined.T_RAddr_(377C)also ok.24. Memory Reference InstructionsMemory reference instructions have a different form from regular instructions, as discussed in thehardware manual. Branch and placement clauses are identical to those in regular instructions, andthe F2 clause, if any, is identical to that in a regular instruction. The rest of the instruction is asingle clause in one of the following forms:PFetch1[RBase, RAddr<, F2>]OddPFetch1[RBase, RAddr<, F2>]PFetch2[RBase, RAddr<, F2>]OddPFetch2[RBase, RAddr<, F2>]PFetch4[RBase, RAddr<, F2>]OddPFetch4[RBase, RAddr<, F2>]PStore1[RBase, RAddr<, F2>]OddPStore1[RBase, RAddr<, F2>]PStore2[RBase, RAddr<, F2>]OddPStore1[RBase, RAddr<, F2>]PStore4[RBase, RAddr<, F2>]OddPStore1[RBase, RAddr<, F2>]IOFetch4[RBase, Device<, F2>]OddIOFetch4[RBase, RAddr<, F2>]IOFetch20[RBase, Device<, F2>]OddIOFetch20[RBase, RAddr<, F2>]IOStore4[RBase, Device<, F2>]OddIOStore4[RBase, RAddr<, F2>]IOStore20[RBase, Device<, F2>]OddIOStore20[RBase, RAddr<, F2>]XMap[RBase, RAddr<, F2>]OddXMap[RBase, RAddr<, F2>]Input[RAddr<, F2><,OtherRAddr>]Output[RAddr<, F2><,OtherRAddr>]ReadPipe[RAddr<,F2><,OtherRAddr>]Refresh[RAddr]IOStore16, OddIOStore16, IOFetch16, and OddIOFetch16 are synonyms for IOStore20,OddIOStore20, IOFetch20, and OddIOFetch20, respectively.In these clauses, "RBase" is an RM address subject to the same constraints as an RM reference in aregular instruction; i.e., it must be in the group of 100 accessible to the current task and must notbe in the subrange 0-17 of that group unless the task selected by SetTask is 0 mod 4; in addition, itmust normally be an even address, as discussed in the hardware manual. When it must be even,you write, for example, "PFetch1[ ... ]"; in the rare case when it must be odd, you write"OddPFetch1[ ... ]." Also, the various forms of RM addressing that require RMod=1 cannot beused when specifying a base register (i.e., Stack, Stack&+n, Stack&-n, PCF[..], SB[..], and DB[..]ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНxО_9sН! НxО]▓НxО[ЙНxОZCНxОX°Н!Т┐П:Т└ Н!ОW;ТїП!Т╗П$Н!ОUзТ▀Т▄П.Н!ОTyНЇОQ+qТП&НxОNis Н!П/НxОLбН!П&НxОKН!НxОIsТ─Н!Т НxОGлН!П'НxОF$ Н!НЇОARrТ÷П"НЇО=ЮqТ╒ТёПEНЇО<Т≤Т≥ПQНЇО:KТ╔ПJТіНЇО8─ТП,НxО5ЎsТ─Н#тТНxО4Т─Н#тТНxО2pТ─Н#тТНxО0хТ─Н#сТНxО/!Т─Н#тТНxО-zТ─Н#тТНxО+рТ─Н#тТНxО*+Т─Н#тТНxО(└Т─Н#тТНxО&эТ─Н#тТНxО%5Т─Н#т ТНxО#▌НxО!ФНxО ?П!НxО≤ НЇОIqТ}П4Т~НЇО~ТП8НЇОТ┘П5Т├П-НЇОBТ≤П2Т≥П3НЇОwТ├П>Т┤П'НЇОґТ╒ПTТёНЇОБТРП5ТСП$НЇО ТїПYТ╗НЇОMТІПb пЇ=Г]LDolphin MicroAssemblerEdward R. Fiala9 October 198128won't work); this is illegal because the DF2 bit in memory reference instructions coincides withRMod in regular instructions.When the optional F2 argument is omitted, the displacement relative to the base register is takenfrom T, and you may use F2 for an unrelated function in a separate clause. If you supply the F2argument, which must be an integer less than 20, that value is stored in the F2 field of theinstruction and used instead of T. See the hardware manual for details on how this works.Note that memory instructions use the ALU to add the low-half base register to the displacement;the result of this addition may be tested in the next instruction if desired. For example, it issometimes useful to branch on the ALU carry in the next instruction, so that the high part of thebase register can be updated when crossing a 64K memory boundary.Input, Output, and ReadPipe references do not use a base register, but address computation is donejust as for other references. "OtherRAddr" (default 0 if omitted) specifies the base register, whichcan be tested by an R<0 or R Odd branch condition in the same instruction, or used to somehowsetup an ALU result for a branch condition in the next instruction. In addition, if the base registeris the target of an immediately preceding PFetch, then the Input or Output will be held until thatreference has finished; specifying a different base register avoids this unnecessary hold--or you candeliberately select the target of the preceding PFetch to interlock the reference.The RAddr argument may be either "Stack" or an RM address accessible to the task. Since thecurrent task is OR'ed into the top 4 bits of the 8-bit SrcDest field that specifies RAddr, RAddr isfurther constrained to satisfy the relation: (RAddr or (CTask lshift 4)) = RAddr. In addition,RAddr must not be 0 (which is the value assembled for "Stack"); for PFetch2/PStore2 it must beeven and for PFetch4/PStore4 it must be quadaligned."Must be even" and "must be quadaligned" are a little too strong. If you violate this rule,the assembler will print a warning message which you are free to ignore. In this case, thehardware will transfer the double-word/quad-word into the two/four RM locationsbeginning with the one you specify and wrapping around at 20-word boundaries (i.e., ifyou specify RM 36 as the address for a PFetch4, the data will be delivered to 36, 37, 20and 21). The reason for the warning is that RM interlocking will not occur correctly, asdiscussed in the next section.25. RM InterlockingThe hardware "interlocks" RM references to ensure that following a memory reference you neitherread an RM word before the memory controller has filled it from storage nor overwrite an RMword before the memory controller has deposited it in storage; an instruction will be repeatedlyaborted and reexecuted until it is safe to proceed. However, the hardware interlock is notfoolproof, so there are some programming requirements of which you must be aware.First, every instruction is reading some RM word (word 0 in the current 100-word region, if youdon't explicitly mention an RM address), but the hardware interlocks reads only when the ALUoperation involves A somehow--no interlock occurs on an LU_T ALU operation, which does notinvolve A. However, sometimes you will utilize an RM word without routing it into the ALU. Forexample:ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТ╦Т╧ПTНЇО]KТНЇОYыТєП)Т╔П8НЇОXТ∙ПBТ√НЇОVDТтТуПMНЇОTyТщТчП>НЇОQТ≤П)Т≥П7НЇОO=ТцТдПTНЇОMrТ⌡П2Т°П/НЇОK╗ТПAНЇОH6Т┤ПFТ┬НЇОFkТ√Т≈ПHНЇОD═Т▒ПRТ▓ НЇОBжТ┴ПQТ┼НЇОAТ≥ПbНЇО?AТ≈Т≤ПNНЇО=vТПRНЇО:ТїТ╗ПSНЇО89Т Т⌡ПNНЇО6oТюП6ТаП)НЇО4єТ⌡Т°ПDНЇО2зТП4НyО/УТ└Т┘ПDНyО.MТ▌П8Т▐П#НyО,іТТПBНyО*ЪТўП&Т╞П0НyО)WТ²Т·П@НyО'╟Т═П<Т║НyО& ТНЇО!rТ÷НЇО║qТ▓Т⌠ПCНЇОжТ╠Т╡ПAНЇОТІП%ТЇП;НЇОAТЛП3ТМП(НЇОvТПQНЇОТїП;Т╗П$НЇО:ТЁП0ТЄП,НЇОoТїПVТ╗НЇО ╔Т└ПJТ┘НЇОз bЇ⌠=Г\x9Dolphin MicroAssemblerEdward R. Fiala9 October 198129StkP_RAddr, RAddr_T;Load an A destination from RAddr, LU_TRAddr, Skip[R Odd];Use the R<0 or R Odd branch conditionsIn these situations, if RAddr is involved in a preceding fetch-type memory reference (PFetch1/2/4,ReadPipe, XMap, or Input) which is still in MC1/MC2, the hardware interlock will not occur andthe instruction will erroneously proceed without waiting for the memory controller to fill the wordfrom storage.The assembler has some features to help avoid programming errors in this situation. First, thedefault ALU operation in an instruction is LU_T, but when you write a clause which loads some Adestination from RM, the default is changed to LU_A which will invoke the read interlock. Inother words:StkP_RAddr;= LU_StkP_RAddr, so the interlock will occurA_RAddr;= LU_A_RAddr, so the interlock will occurRAddr, Skip[R Odd];didn't say A_RAddr, so LU_T is still the default and interlock willNOT occur--potential undetected programming error here.StkP_RAddr, RAddr_T;LU_A default overruled by LU_T, so no interlock will occur, but theassembler will issue a "No register interlock" warning to you in this case;you can ignore the warning if you want to, but...StkP_RAddr, RAddr_T, NoRegILockOK;suppresses the "no register interlock" warning message; you should addthe "NoRegILockOK" clause to instructions which do not invoke theregister interlock if you are sure that not having the register interlock isok.Another set of potential problems occurs when the two RM words involved in PFetch2/PStore2 arenot an even-odd pair or when the four RM words affected by a PFetch4/PStore4 are notquadaligned (i.e., the first of the four words does not have two low zeroes in its address). Forexample, suppose a PFetch2/PStore2 is made to the Stack; if the first of the two RM words is even,all is well and the hardware interlock will abort references to either of the two words involved inthe reference; however, if the first of the two RM words is odd, then the hardware will NOT abortreferences to the second word involved in the reference (It will instead erroneously abort referencesto the RM word preceding the first word). Similar problems occur when the first RM word of aPFetch4/PStore4 is not quadaligned.To assembler will flag potential problems in these situations with a warning message "WARNING:RAddr not even" on a PFetch2/PStore2 or "WARNING: RAddr not quadaligned" on aPFetch4/PStore4 for which the RM address is not aligned. These warning will not occur onPFetch2/PStore2 to the stack. If an unaligned reference is legitimate, then you must advise theassembler by placing an "OddOK" or "NonQuadOK" clause to the right of the reference.When you reference a stack word that is potentially the second word of an unaligned andincomplete PFetch2, you have to be very careful to use the Stack&-n form of reference; when youwrite any stack word that is potentially the second word of an unaligned and incomplete PStore2,you must use the Stack&+n form of reference. Also note that when you interlock by usingStack&-n or Stack&+n, you do not have to route the stack through the ALU to accomplish theinterlock. These are discussed in the hardware manual.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНxО_9sТ─Н!ТП"НxО]▓Т─Н!ТП#НЇОZCqТ▒Т▓ПZНЇОXxТ≤Т≥ПLНЇОVўТ≤Т≥ПCНЇОTЦТНЇОQqТҐП'ТЎП8НЇОOїТ└ Т┘ПTНЇОMэТ╞П]НЇОLТНxОIPs Н!П,НxОG╗Н!П)НxОFТ─Н!ТбП*ТцН!ОD═ТП7НxОBЫТ─Н!Т╔П+ТіН!ОA≤Т│П@Т┌ Н!О@7ТП1НxО>░Т─П"Н!О=/ТёП;Тє Н!О;оТцП=ТдН!О:nТ∙П?Т√Н!О9 НЇО5ЎqТ┴ Т┼ПPНЇО3ТТЖПTНЇО2)Т╣ТІПOНЇО0_Т┐П\Т└НЇО.■Т║П?Т╒П$НЇО,иТ▄ПaНЇО*ЪТ▀П7Т▄П.НЇО)4Т÷ПPТ═НЇО'iТП#НЇО#ЬТ░П2Т▒П,НЇО"-ТПHТНЇО bТсП+ТтП.НЇО≤ТЄП\Т╣НЇОмТЭТЩП@НЇО[ТПТЯП8Н?╔ОЧЗО[НЇО:ЧВО▒Т■П!Н+ГО:ЧІО▒П"Т∙НЇОфТ═Т║П6Н3:ОoЧ ОфНЇОШТяНkОєЧнОШП"ТрП!НЇО1ТґП(ТўП2НЇОfТП7■Ї=ГWЛqDolphin MicroAssemblerEdward R. Fiala9 October 19813026. Standalone FunctionsThe following summarizes standalone functions, each written as a separate clause in the instruction:BreakPointCauses the instruction to be breakpointed by Midas when debugging.NopAssembles a no-op instruction.SpareFunctionUses F1 and F2 (undefined)ResetErrorsUses F1 and F2IncMPanelUses F1 and F2ClearMPanelUses F1 and F2GenSRClockUses F1 and F2ResetWDTUses F1 and F2BootUses F1 and F2SetFaultUses F1 and F2ResetFaultUses F1 and F2UseCTaskUses F1 and F2WriteCS0&2Uses F1 and F2WriteCS1Uses F1 and F2ReadCSUses F1 and F2D0OffUses F1 and F2RegShiftUses F2 (ordinarily not written explicitly becuase the sources that requireit are individually named, so you probably will never use this)FreezeResultUses F2IOStrobeUses F2ResetMemErrsUses F2UseCOutAsCInUses F2SkipDataSee the "NextData and NextInst" section.CSkipDataSee the "NextData and NextInst" section.LoadPage[n]Uses F1 and F2; 0 <= n <= 17, where n is an integer equal to thepage number; this is used when an ordinary branch clause is used in thenext instruction.LoadPageExternal[n]Like LoadPage; this must be used when the branch clause in the nextinstruction is a GotoExternal or CallExternal.At[n1,n2]See the "Placement Declarations" section.Opcode[n]See the "Placement Declarations" section.27. BranchingThis section discusses branch and dispatch clauses, which are assembled into the JC and JA fields ofthe instruction. At assembly time, D0Lang produces the correct JC field and sometimes the correctJA field or correct low bit of JA; however, most branch clauses indicate the required branchlinkages in extra fields assembled only for MicroD. MicroD then determines a satisfactoryplacement for the instructions and fills out JA correctly.The hardware defines GoTo, Call, Disp, Return, and conditional GoTo, each represented by codesin the JC instruction field; conditional GoTo's may specify any of eight branch conditions usingonly JC and JA or 6 more branch conditions using F2. The least significant bit of JA is used tomodify the branch condition on a conditional GoTo and to modify the action of a Return.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷НЇО[]qТ█П.Т▌П6НxОX°s Н!ТбП7Тц НxОVТН!ТНxОUMН!НxОSі Н! НxОQЧН! НxОPW Н! НxОN╟ Н! НxОMН! НxОKaН! НxОI╨Н! НxОH Н! НxОFkН! НxОDд Н! НxОCН! НxОAuН! НxО?нН! НxО>&Н!Т┤П2Т┬Н!О<фТП?НxО;Н!НxО9wН!НxО7пН!НxО6(Н!НxО4│Н!П(НxО2зН!П(НxО12 Н!Т∙Т√П/Н!О/яТ├П8Т┤Н!О.qТНxО,иН!Т╔П>ТіН!О+iТП.НxО)аН!П)НxО(Н!П)НЇО#GrТ÷ НЇОуqТ─Т│ПNНЇОТ┼ПLТ▀НЇО@ТсП"ТтП:НЇОuТУП"ТЖП8НЇО╚ТП:НЇО9Т√Т≈ПRНЇОnТ╠Т╡ПZНЇОєТ÷Т═ПOНЇОыТГП8ТХЪhЇ▓=ГXy3Dolphin MicroAssemblerEdward R. Fiala9 October 198131The assembly language encodes these possibilities in the following kinds of branch clauses:DblGoTo[t1, t2, bc]Jumps to t1 if the branch condition bc is true, else to t2; MicroD willplace t2 at an even location and t1 at the adjacent odd location; thetargets must be on the same 400-word microstore page as the instructioncontaining the DblGoto.GoTo[t1<, bc>]Jumps to t1 if the optional bc is either omitted or true, else falls throughto the next instruction inline. t1 will be placed on the same page as thecurrent instruction. If bc is given, the next instrucion inline will beplaced at an even location and t1 at the adjacent odd location.Skip[]= GoTo[.+2<,bc>]Call[t1]Loads TPC[current task] with the address of the next instruction inlineand branches to t1; MicroD will place the next instruction inline at (. &7760)+(.+1 & 17) and will place t1 on the same page.CallX[t1]Loads TPC[current task with (. & 7760)+(.+1 & 17) and branches to t1.The next instruction inline is not constrained to lie at any particularlocation; MicroD will place t1 on the same page.Disp[t1]Will dispatch to the the table origined at (t1 & 7760); the programmermust manually place all instructions in the dispatch table with At clauses.The dispatch will transfer control to (t1 & 7760) OR'ed with the lowfour bits of APC. The instruction immediately preceding Disp mustnormally be a Dispatch (but conceivably UseCTask or APCTask&APC_might be used instead of Dispatch in some clever situations).ReturnReturns to the address in APC (JA.7=0).NIRetReturns to the address in APC (JA.7=1) which will contain2001+(4*ByteCode); this form of return is used after NextInst.TaskSpecial kludge that does Call[.+1] in the current instruction and forces aReturn in the next instruction inline (which must not have any branchclause); the second instruction inline will be placed at .+1.GoToExternal[n]Puts a goto code in JC and stores the integer n in JA; no placementconstraints imposed and no error checking; usually used afterLoadPageExternal[m].CallExternal[n]Puts a call code in JC and stores the integer n in JA; no placementconstraints imposed and no error checking; usually used afterLoadPageExternal[m].DblGoToP[t1, t2, bc]= DblGoto with the on-page constraints removed; the precedinginstruction must contain an apropriate LoadPage; no error checking.GoToP[t1, bc]= Goto with the on-page constraint removed.CallP[t1]= Call with the on-page constraint removed.DispP[t1]= Disp with the on-page constraint removed.SkipP[t1]= Skip with the on-page constraint removed.In the above forms, t1 and t2 may be instruction labels or one of the following special symbols:.+3current address + 3..+2current address + 2..+1current address + 1..the address of the current instruction..-1current address - 1..-2current address - 2..-3current address - 3.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qТЧПBТЪНxО\TsТ─Н!Т²Т·П.Н!ОZСТ╣ПAТІН!ОY⌠Т▐П;Т░Н!ОX2ТНxОV┼Т─ Н!Т│Т┌ПAН!ОU*Т├Т┤П3Н!ОSиТЎП9Т©Н!ОRhТП?НxОPа Н!НxОOН!Т╙Т╚П0Н!ОM╧Т▄Т█П:Н!ОLXТП4НxОJ╠Н!Т├ПAТ┤Н!ОIPТбТцП)Н!ОGОТП0НxОFHН!Т·П*Т÷Н!ОDГТ└П'Т┘П$Н!ОC├ТЁП+ТЄН!ОB%ТдТеП6Н!О@еТ·П0Т÷Н!О?dТП=НxО=╪Н!П'НxО<Н!ТDТEН!О:ЄТП>НxО9 Н!Т┴П%Т┼П%Н!О7╛Т╔П1ТіН!О6KТП=НxО4єН!Т╚ПCН!О3CТHТIП*Н!О1ЦНxО0;Н!ТЁП6ТЄН!О.зТHТIП*Н!О-zНxО+рТ─Н!ТП<Н!О*rТъТЮП+НxО(йТ─Н!ТП*НxО'#Н!П+НxО%|Н!П+НxО#тН!П+НЇО ├qТ╚ПOТ╛НxОдsН!ТНxОН!НxОuН!НxОнН!П'НxО'Н!НxОН!НxОьН!8Ї╣<ГTVtDolphin MicroAssemblerEdward R. Fiala9 October 198132Branch conditions may be any of the following:RegularComplementaryALU#0ALU=0CarryCarry'ALU<0ALU>=0H2Bit8'H2Bit8R<0R>=0R OddR EvenIOAtten'IOAttenMBMB'IntPendingIntPending'Uses F2Ovf'OvfUses F2BPCChkBPCChk'Uses F2QuadOvfQuadOvf'Uses F2TimeOutTimeOut'Uses F2The complementary form of the branch conditions is provided as a programming convenience. Theeffect of using a complementary branch condition is to interchange the even-odd constraints on thetarget pair.28. NextData and NextInstThe assembler contains a number of macros and placement features to support the NextData andNextInst hardware functions. These functions trap to absolute location 0 in the microstore whenthe quadword buffer containing data from the opcode stream is exhausted; on a trap, the instructionaddress in CIA will be saved in TPC iff the instruction containing NextData/NextInst has a Callencoded in its JC field.The system microcode deals with this situation as follows: First, the trap instruction at 0 contains a"LoadPageExternal[0], GoToExternal[377]" where the GoTo sends control to location 377 on the pagecontaining the NextData/NextInst that trapped. Next, the instruction at 377 on that page will contain a"PFetch4[PC,IBuf,4], GoToP[BufferRefill]" or whatever, where BufferRefill is on page 0. There are restrictionson what can be done by the trap instruction at location 0 (see hardware manual).For this reason it is usually necessary to encode a Call in JC to ensure that the trap subroutine willrestart at the correct place. However, this will usually be a "fake call" (equivalent to CallX) becausethere is no intention to return from a subroutine to .+1 in the instruction stream. Consequently,the assembler has a bit in its output data format (the OddCall bit) which tells MicroD that, eventhough the current instruction contains a call, it is not necessary to place the next instruction inlineat .+1 in the microstore. Some of the macros discussed below set this bit to avoid imposing anunnecessary placement constraint on the program.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qП.НxО\TuНнНxОYІsНнНxОXНнНxОVgНнНxОTюНнНxОSНнНxОQqТ─НнТНxОOйНнНxОN#НнНxОL{ Нн Н#уНxОJтНнН#уНxОI-НнН#уНxОG┘НнН#уНxОEчНнН#уНЇОB▐qТ├Т┤ПEНЇО@еТ░П[Т▒НЇО>ЗТНЇО:rТ÷НЇО6▓qТёП7ТєП%НЇО4гТ╙П-Т╚П3НЇО2ЩТ│П=Т┌П&НЇО12Т╘ПXТ╙НЇО/hТНyО,іsТъП[ТЮ НyО+EТГП(ТХП9НyО)ДТЇП^Т╦ НyО(└Т└ПTТ┘НyО'#ТПPНЇО#тqТ┼П*Т▀П<НЇО" Т─П<Т│П,НЇО ?Т·П&Т÷П<НЇОtТёТєПTНЇО╙Т░ПhНЇОъТїТ╗ПRНЇОТП0&Їн=ГO=Dolphin MicroAssemblerEdward R. Fiala9 October 198133The macros defined for these two functions are as follows:A_NextInst[RAddr]Instruction dispatch on the next opcode in the opcode stream;PCF[RAddr] addressing selects the word in the quadword-bufferbeginning at RAddr containing the next byte; the NextInst F1 functioncauses the cycler-masker to select the byte in that word according to thelow bit of PCF; forces a fake Call to be encoded in JC. No branchclause is necessary if the successor is the next instruction inline, but ifany branch clause is specified, it must be a (fake) Call or CallX.A_CNextInst[RAddr]Like NextInst, but the JC field is not constrained and any branch clausemay be used. However, unless either a buffer refill trap is impossible(because the BPCChk branch condition is false or because PCF is knownto be odd) or the return address in TPC has already been setup to copewith a trap, you will have to write an explicit Call into the instruction toensure that a buffer refill trap will return to reexecute this instruction;this will be a real call.A_NextData[RAddr]Like NextInst but uses the NextData function rather than the NextInstfunction to obtain the next byte in the opcode stream.A_CNextData[RAddr]Like CNextInst but uses the NextData function.SkipDataUses the NextData function to skip the next byte in the opcode streamwithout referencing it; forces a fake Call to be encoded in JC; does notimpose PCF addressing, so any RM address can be referenced (butbecause the NextData function will use the cycler-masker to select eitherthe left or right byte of the selected RM address, your use of that RMaddress is limited).CSkipDataLike SkipData, but does not impose any constraint on JC; any branchclause may be used. If the branch clause is a Call, it will be "real" andthe successor will be the next instruction inline; if not a Call, you mustbe sure that either a trap is impossible or the return address already inTPC is an appropriate return from the trap subroutine.Here are some examples using these macros:LU _ NextInst[IBuf];*Successor to NextInst is .+1Push:Stack&+1 _ T, NIRet;LU _ NextInst[IBuf], Call[Push];*Successor to NextInst is at the label "Push"T _ CNextData[IBuf], Call[FixPointer];*Real call with NextData functionT _ (Stack&-1) + T, GoTo[Push];Call[FixT];*Call unnessary because return for possible trapT _ CNextData[IBuf], Skip[IntPending];*already setupLU _ Cycle&PCXF, FreezeResult, Skip[R Even]; CSkipData, DblGoTo[A,B,ALU<0];*Trap impossible because PCF is oddDblGoTo[A,B,ALU<0];Note: It is not strictly necessary for NIRet to occur in the instruction immediately after theNextInst/CNextInst. From the hardware manual, it appears that a subroutine which returned bydoing a NIRet could intervene. In other words, the NextInst could be followed by an arbitrarycode sequence; when NIRet occurred, the dispatch address for the next opcode would be put intoTPC; and the Return or NIRet after that would send control to the next opcode.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО_qП:НxО\TsН!Т%П=Н!ОZСТ2П=Н!ОY⌠Т═П0Т║Н!ОX2Т▐П&Т░П#Н!ОVяТ╗Т╘П3Н!ОUpТіТїП1Н!ОTТАПBНxОRhН!Т▄П&Т█П"Н!ОQТіП9Тї Н!ОOїТ├П-Т┤Н!ОNFТ▀ Т▄П<Н!ОLЕТ┘П4Т├Н!ОK└ТїП>Т╗Н!ОJ#ТНxОH|Н!ТіТїП/Н!ОGТП6НxОEtН!П.НxОCмН!Т П>Т⌡Н!ОBlТ░Т▒П5Н!ОAТр ТсП5Н!О?╙Т░П"Т▒П'Н!О>JТ≈Т≤П0Н!О<ИТНxО;AН!Т╗Т╘П,Н!О9АТ┤ПFТ┬Н!О8─Т■П9Т∙Н!О7Т≤Т≥П6Н!О5ЎТП6НЇО2pqП*Н╛О/ўsТ─Н, ТНxО.MН╛Н╛О,Т─Н, ТЩТЧН╛О)ДТ─П&Н,ТН╛О(└Н╛О&O Н,ТтТуП!Н╛О$НТ─П&Н,ТН╛О"╨П,Н╛О!YТ─Н,ТН╛ОЬНЇО╙pqТуПVТжНЇОъТ╘Т╙ПIНЇОТ╟П(Т╠П6НЇОJТ ПYТ⌡НЇОТПNЪЄЇ8=ГRсcDolphin MicroAssemblerEdward R. Fiala9 October 19813429. Placement DeclarationsCurrently, you must specify the page on which each instruction is placed. This is done by adeclaration of the form:OnPage[n];where the integer n is the page number (0 to 17). Subsequently assembled instructions will beplaced on the specified page. The OnPage declaration may appear only as a separate statement.Two other declarations may appear only as clauses in an instruction being assembled; these specifythe exact placement of the instruction and also do OnPage, so that subsequently assembledinstructions will be placed on the same page. These are:At[n1]places the current instruction at location n1.At[n1, n2]places the current instruction at location n1+n2.Opcode[n]places the current instruction at 2001+(4*n), where n is the opcode (0 to 377)DispTable[Length,Mask,Value] appearing in an instruction statement causes that instruction to begina group of Length consecutively-placed statements, where 1 <= Length <= 20. The firstinstruction will be placed at a location such that And[location,Mask] = Value, where Mask defaultsto 17 and Value to 0. It is required that Length+Value be less than 21. Placement of theinstruction containing DispTable will be further constrained by whatever OnPage declaration is inforce.Note that DispTable will not handle all dispatch tables; it requires that a table be no longer than 20with no "holes" and that the instructions in the table appear as consecutive statements in the sourceprogram. Whenever these conditions cannot be met, At clauses must be used for the instructions inthe table.Opcode declarations are required for the entry instructions of opcodes; At declarations are requiredfor trap instructions, for instructions in dispatch tables that cannot use DispTable for some reason,and in a few other situations, but MicroD will take care of normal placement constraintsautomatically.To assist in defining absolute locations for dispatch tables and manually placed instructions the"LOCA" macro is defined:Loca[Name,Page,Offset]defines Name as an integer equal to Page*400 + Offset, where Page and Offset areintegers.In addition to the above placement declarations, there are two macros for "reserving" or"unreserving" locations in IM. These macros, which direct MicroD to avoid placing instructions inparticular microstore locations, are as follows:IMReserve[p,w,n]where p, w, and n are integers reserves n locations beginning at word w on page p.НЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷НЇО[]qТкП2ТлП*НЇОY⌠ТНyОVяs НЇОS┌qТ╧П2Т╨П,НЇОQ╦Т╞П^НЇОNFТ⌠ПCТ■НЇОL{ТТПOТУ НЇОJ╠ТП9НxОGОsН░П.НxОFHТ─ Н░ТП+НxОD═Н░ТЎПFТ©НЇОARqТ┤П,Т┬П7НЇО?┤ТАТБПOНЇО=╪Т▄ПNТ█НЇО;РТоТпПAНЇО:'Т╔ПHТіНЇО8]НЇО4КТ┐ПIТ└НЇО3 Т┤П^Т┬НЇО1UТ┘П_Т├НЇО/▀Т НЇО,Т█П$Т▌П@НЇО*NТ≥П:Т П+НЇО(└ТТПRНЇО&╧ НЇО#GТцТдПUНЇО!}ТНxО╩sН░Т├Т┤П>Н░ОZНЇОqТП0ТП(НЇОAТ░ПRТ▒НЇОvТП0НxО╣sН░Т┤ПEТ┬ ╨Ї▓=ГTy Dolphin MicroAssemblerEdward R. Fiala9 October 198135IMUnReserve[p,w,n]unreserves n locations beginning at word w on page p.For diagnostics, the declaration statement "MidasInit;" may be issued to reserve the severallocations on page 0 and all of page 17 for use by the debugger Midas.30. Tasking ConsiderationsSince task switching occurs only when an "unrestricted" return is executed, each task must be sureto execute instructions containing returns often enough to satisfy the timing requirements of taskswhich are higher (or sometimes lower) in priority. Here "unrestricted" means that the instructionpreceding return did not do APCTask&APC_ or UseCTask, which disallow task switching.When an unrestricted return is executed, the highest priority different task requesting service willrun, or the emulator if no other tasks are requesting. This has several implications:First, when a high priority task such as the display driver executes a return when it has not yetblocked, it will lose control to some other task (usually the emulator) until that task does a return.This means that it should not do too many returns else the accumulated interference of lowerpriority tasks will add up to so large a value that its timing requirements are not satisfied.Secondly, each task must be sure to execute Returns frequently enough that higher priority tasksreceive adequate service.We can illustrate this with an example. Suppose that the timing requirement of the display driver isthat upon issuing a wakeup request it be granted 88 cycles out of the next 288 cycles and that itexecutes one intermediate return before its final return after blocking. Initial service will be delayeduntil whatever task is running executes a return, and further delayed until all higher priority tasksare satisfied. At the intermediate return, a lower (or higher task) will run first and then higher tasksuntil they are satisfied. If page or write protect faults or single-error logging are possible, thensome allowance must be made for the fault task, which has a long burst of non-tasking computationat the beginning of each fault. The total interference of all these other tasks must be less than 200cycles.The emulator task for the current AMesa system microcode attempts to satisfy this requirement bytasking at least once every 46 cycles.Another programming consideration is the exact placement of returns. It is frequently possible tochoose one of several places; one good place is immediately before an instruction that will beaborted--e.g., before an instruction that will read an RM word for which a PFetch has just beenstarted or write an RM word for which a PStore has just been started. An undesirable placement iswhere the current task could proceed because it is not issuing memory references but where anothertask might experience an abort because MC1 is busy.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНxО_9sН░П5НЇО[ЙqТВП\НЇОZ ТПEНЇОU*rТ÷НЇОQ╦qТ∙ПUТ√НЇОOМТ╔ПBТіП!НЇОN#Т÷Т═ПRНЇОLXТПTНЇОHФТ╞П>pqТ╟НЇОGТПVНЇОC╘Т╟ПMТ╠НЇОAъТ√П9Т≈П-НЇО@ТиП:ТйП"НЇО>JТЙПOТКНЇО:ьТ╚Т╛П@НЇО9 ТНЇО5⌡Т─П5Т│П0НЇО3пТєП%Т╔П<НЇО2Т─П'Т│ПBНЇО0;Т·ПeНЇО.qТ│ПMТ┌НЇО,іТ╦П"Т╧ПCНЇО*шТ┘Т├ПBНЇО)Т▌Т▐ПGНЇО'FНЇО#тТ√П8Т≈П(НЇО" ТП&НЇО≤Т÷ПVТ═НЇОмТиПEТйНЇОТґП.ТўП1НЇО8Т┘П'Т├П;НЇОmТ└П>Т┘П$НЇОёТП3Ъ4Ї\>ГR╞Dolphin MicroAssemblerEdward R. Fiala9 October 19813631. Microcode OverlaysThe barest minimum provisions are made for microcode overlays. When assembling basic systemmicrocode, the IMReserve macro discussed in the "Placement Declarations" section may be used todisallow the use of any set of IM locations by MicroD. Also, any pages totally unused by thesystem microcode or containing throwaway initialization code are available to overlays. Finally,particular instructions in the system overwritten by particular instructions in an overlay must bemanually placed with "At" declarations in both the system microcode and the overlay.An overlay must use IMReserve to prevent its use of any locations on pages that it shares withsystem microcode. MicroD has a switch that will write a xxOccupied.Mc file containing IMReservestatements.Any instructions in the system branched to from an overlay must be manually placed with "At" andvice versa. Then, instead of using LoadPage[n] and GoTo[n] or Call[n], you must useLoadPageExternal[n] and GoToExternal[n] or CallExternal[n] in instructions that branch between thesystem and an overlay.32. Recent Hardware and Assembler Changes1.SUB, EQUATE, ASMMODE, TRACEMODE, and WHILE Micro builtins and the "warning"code for the ER builtin.2.Some names have been assigned to R-bus sources that were formerly referred to byGetRSpec[n] phrases (e.g., Cycle&PCXF, SStkP&NStkP, CTask&NCIA, Page&Par&Boot,ALUResult&NSALUF).3.Bugs in use of GoTo with read/write control store were fixed.4.Some error messages for PFetch2/PStore2 and PFetch4/PStore4 were changed to warnings, andthe OddOK and NonQuadOK clauses to the right were added to overrule the warnings.5.The specification of a second RM address with Input[..], Output[..], and ReadPipe[..].6.OddBaseOK was removed and OddPFetch1, etc. were recently added.7.SkipData, CSkipData, CNextInst, Loca, IMData, HiA, LoA, RV2, RV4, CallX, negativeconstants, Formn, Form-n, and Nib0RSh8, andIF, UNLESS, ELSEIF, ELSE, ENDIF conditionalassembly stuff are recent assembler additions.8. The IMMASK memory handled by MicroD and the DispTable macro which outputs placementconstraints for dispatch tables are new.9. Additional MicroD output files.ЪНЇОf╙pТ─Н!цqН4]ТНG╘ОfЯpНЇО^оrТ÷НЇО[]qТ╒ ТёПRНЇОY⌠Т▄Т█ПAНЇОWхТ╧П6Т╨П'НЇОUЩТаПaНЇОT3Т╪ПRТҐНЇОRhТПTНЇОNЖТЄТ╣ПKНЇОM,Т┼Т▀ПCНЇОKa НЇОGОТ┌Т┐ПPНЇОF$Т&П>Т'НЇОDZТ─П^Т│НЇОB▐ТНЇО=≥rТ÷П*НЇО:'qН2Т║ПAТ╒ НЇО8]ТНЇО4КН2ТП&ТП*НЇО3 Т╔П&ТіП(НЇО1UНЇО-ДН2ТП=НЇО*rН2Т▀Т▄ПBНЇО(їТПQНЇО%5Н2ПVНЇО!цН2П?НЇОQН2Т ПHТ НЇО┤Т─П+Н){Т╒ТёНЇО╪ТП.НЇОJТ≥П8Т НЇОТП(НЇО П#ўЇф=ГVEР HELVETICA TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN╒эЛдТ"б*А17А>:BшJ%OUС\bgъiЕq%wЪ~Д┘Я▄Н⌠≈ Й÷єЄ╚ гЄ ▐Ґмд▄лНс²шВБШЙПіB "┌ └┘┼" ic"┐B":ДJЛ%39ZФ)YЯЪЖ╘╙&╚ZЬ В")&iВ%9iФ #B"┌ No default fontБiX":C:#:;Ф Nd"═B"┌P:C!T:C!Q:C":C!L:C%а:C":C┘P:C%Є:C!Є:CЖ#j/С%ЯЪЪ≈Н2▀ЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪD0Microassembler.PressFiala 9-Oct-81 16:15:23 PDTЯ