[Cyan]<D0>testerdrawings.disk!1>d0en01.ps

SIGNAL NAMES:

+: 1(1) 2(1) 3(1) 4(1) 5(1) 6(1)
7(1) 8(1) 9(1)10(1)11(1)12(1)
13(1)14(1)15(1)16(1)17(1)
AdvPipe’: 2(1)
AltoEtherID.00: 8(1)16(2)
AltoEtherID.01: 8(1)16(2)
AltoEtherID.02: 8(1)16(2)
AltoEtherID.03: 8(1)16(2)
AltoEtherID.04: 8(1)16(2)
AltoEtherID.05: 8(1)16(2)
AltoEtherID.06: 8(1)16(2)
AltoEtherID.07: 8(1)16(2)
AltoEtherID.08: 8(1)16(2)
AltoEtherID.09: 8(1)16(2)
AltoEtherID.10: 8(1)16(2)
AltoEtherID.11: 8(1)16(2)
AltoEtherID.12: 8(1)16(2)
AltoEtherID.13: 8(1)16(2)
AltoEtherID.14: 8(1)16(2)
AltoEtherID.15: 8(1)16(1)17(1)
AltoEtherID.16: 7(1)16(1)17(1)
BadAlignment’: 5(1) 6(1)
BadCRC: 6(1)
BadCRC’: 5(1) 6(1)
BadParity’: 11(1)12(1)
Carrier: 5(1) 6(2)15(2)17(1)
Carrier’: 6(1)11(1)15(1)
CarrierEM: 15(4)17(1)
CC: 15(2)
CD: 15(2)
CD’: 15(2)
Collision: 12(1)15(1)
CollisionEM:15(2)
CR: 15(2)17(1)
CRCMode: 11(3)
CRCMode’: 11(2)
CRCReset: 6(1)
CTask.0: 1(1)
CTask.1: 1(1)
CTask.2: 1(1)
CTask.3: 1(1)
CTask=15’: 1(1)13(2)
CTask=ITask’: 1(1) 7(1)13(2)
CTask=OTask’: 1(1) 7(1)13(2)
DblCk: 14(1)
DCk: 15(2)
DCkDly: 15(2)
Disableb17: 13(1)17(1)
Disableb9: 11(1)17(1)
Disablec9: 11(1)17(1)
Disablef13: 9(1)17(1)
Disableh10: 3(1)17(1)
DoneWithInPacket’: 2(1) 3(1) 5(1) 7(2)
DoneWithOutPacket:11(2)
dTx’: 13(1)
EdgeClock’/a: 2(3) 3(2)12(1)
EdgeClock’/b: 3(2) 7(1) 9(2)10(1)12(1)
EdgeClock’/c:10(1)12(3)13(2)
EdgeClockFeed’:12(1)
EnableBadParity:11(1)
EnableInWake’:13(2)
EnableJam: 2(1) 7(1) 8(1)14(1)
EnTClk’: 14(1)17(1)
ExcessCount.0: 3(1) 7(1) 8(1)
ExcessCount.1: 3(1) 7(1) 8(1)
G1: 13(1)
G123P1: 13(2)
G1P1: 13(1)
G1P2: 13(1)
G2: 13(1)
G23P1: 13(2)
G2P1: 13(1)
G2P2: 13(1)
G3: 13(1)
G3P1: 13(2)
G3P2: 13(1)
GND: 1(7) 2(2) 3(1) 4(7) 5(2) 6(5)
7(6) 8(13) 9(1)10(3)11(4)12(6)
13(4)14(5)15(7)16(5)17(3)
Gnd: 1(1) 2(1) 3(1) 4(1) 5(1) 6(1)
7(1) 8(1) 9(1)10(1)11(1)12(1)
13(1)14(1)15(1)16(1)17(1)
IAddr.0: 1(1)
IAddr.1: 1(1)
IAddr.2: 1(1)
IAddr.3: 1(1)
IAddr.4: 2(1)
IAddr.5: 2(1)
IAddr.6: 2(1)
IAddr.7: 2(1)
IAddr6’: 2(2) 7(1) 8(8)
IAddr7’: 2(2) 7(1) 8(8)
IAddr=ITask: 1(1) 2(3) 8(1)
IAddr=OTask: 1(1) 2(2) 7(1)
IData.00: 8(1)
IData.01: 8(1)
IData.02: 8(1)
IData.03: 8(1)
IData.04: 8(1)
IData.05: 8(1)
IData.06: 8(1)
IData.07: 8(1)
IData.08: 8(1)
IData.09: 8(1)
IData.10: 8(1)
IData.11: 8(1)
IData.12: 8(1)
IData.13: 8(1)
IData.14: 8(1)
IData.15: 8(1)
IData.16: 7(1)
IH: 15(4)17(1)
IH’: 15(2)
IMe’: 2(1)
IMeF’/a: 2(1) 7(1) 8(2)
IMeF’/b: 2(1) 8(2)13(1)
InAttnReq: 3(1) 5(1) 7(1)
InBuffAddr.0’: 3(1) 4(1) 5(1)
InBuffAddr.1’: 3(1) 4(1) 5(1)
InBuffAddr.2’: 3(1) 4(1) 5(1)
InBuffAddr.3’: 3(1) 4(1) 5(1)
InCAddr.0’: 1(3)13(1)
InCAddr.1’: 1(3)13(1)
InCAddr.2’: 1(3)13(1)
InCAddr.3’: 1(3)13(1)
InCAddrReady:13(3)
InData.00: 4(1) 8(1)
InData.01: 4(1) 8(1)
InData.02: 4(1) 8(1)
InData.03: 4(1) 8(1)
InData.04: 4(1) 8(1)
InData.05: 4(1) 8(1)
InData.06: 4(1) 8(1)
InData.07: 4(1) 8(1)
InData.08: 4(1) 8(1)
InData.09: 4(1) 8(1)
InData.10: 4(1) 8(1)
InData.11: 4(1) 8(1)
InData.12: 4(1) 8(1)
InData.13: 4(1) 8(1)
InData.14: 4(1) 8(1)
InData.15: 4(1) 8(1)
InDataParity: 5(1) 7(1)
InDiff#0: 2(1) 3(1)
InDiff=15’: 3(2)
InDiff>3: 3(1)
InEOP: 5(1) 7(1)
InhibitC: 15(2)
InhibitR: 15(2)17(1)
InputEOP’: 2(1) 3(1) 4(1) 5(2)
InSRC=15’: 6(2)
InStatus.0: 5(1) 7(1) 8(1)
InStatus.1: 5(1) 7(1) 8(1)
InStatus.2: 5(1) 7(1) 8(1)
InStatus.3: 5(1) 7(1) 8(1)
InWakeReq’: 3(1)13(2)
IOAttn’: 7(1)
IReq’: 7(1)
ISync: 7(1)
IVal: 2(2)
IValid’: 2(1)
Jam: 11(1)12(1)14(1)
JC: 14(1)15(1)
JR: 14(1)15(1)17(1)
LastRClock: 6(1)15(2)
LC: 15(2)
Line’: 6(1)11(1)15(2)
LoadOutSR: 11(2)
LoadPostIB’: 4(1) 5(1) 7(1)
LoadPream: 11(2)
LoadPreIB: 4(1) 5(1) 6(1) 7(1)
LoopBack: 2(1) 7(1) 8(1)15(1)
LoopBack’: 2(1)12(1)14(1)15(1)
LR: 15(2)17(1)
MC2StartXport: 2(1)
OAddr7’: 2(4)
OAddr=ITask: 2(2)
OAddr=OTask: 2(2)
OData.00: 10(1)
OData.01: 10(1)
OData.02: 10(1)
OData.03: 10(1)
OData.04: 10(1)
OData.05: 10(1)
OData.06: 10(1)
OData.07: 10(1)
OData.08: 10(1)
OData.09: 10(1)
OData.10: 10(1)
OData.11: 10(1)
OData.12: 10(1)
OData.13: 10(1)
OData.14: 10(1)
OData.15: 10(1)
OData.16: 10(1)
OFault’: 12(1)
OKtoTransmit’:11(2)
OMe’: 2(2)
OMeF: 2(3)12(1)
OMeF’: 2(1)13(1)
OReq’: 12(1)
OutAttnReq: 7(1) 9(1)11(1)
OutBuffAddr.0’: 9(1)10(1)
OutBuffAddr.1’: 9(1)10(1)
OutBuffAddr.2’: 9(1)10(1)
OutBuffAddr.3’: 9(1)10(1)
OutCAddr.0’: 1(3)13(1)
OutCAddr.1’: 1(3)13(1)
OutCAddr.2’: 1(3)13(1)
OutCAddr.3’: 1(3)13(1)
OutData.08: 2(1)10(1)
OutData.09: 2(1)10(1)
OutData.10: 2(1)10(1)
OutData.11: 2(1)10(1)
OutData.12: 2(1)10(1)
OutData.13: 2(1)10(1)
OutData.14: 2(1)10(1)
OutData.15: 2(1)10(1)
OutDataParity’:10(1)11(1)
OutDataParitySync:11(1)
OutDiff=0: 9(1)11(1)12(1)
OutDiffLE11: 9(1)11(1)
OutputEOP: 2(1) 7(1) 8(1)
OutputEOP’: 2(1) 9(1)11(1)12(1)
OutSRC=15: 11(2)
OutStatus.0: 7(1) 8(1)12(1)
OutStatus.1: 7(1) 8(1)12(1)
OutStatus.2: 7(1) 8(1)12(1)
OutStatus.3: 7(1) 8(1)12(1)
OutWakeReq’: 9(1)13(1)
OValid’: 2(1)
OverRun: 3(2)
OverRun’: 3(2) 5(1)
PacketInMode: 3(1) 6(3)
PacketInMode’: 6(2)
PacketOutMode:11(4)
Ph1: 13(2)
Ph1Next’: 13(4)
Phase1’: 13(4)
Phase1Next’:13(1)
PktInModeSync: 3(2)
PostIBFull: 2(1) 3(1) 7(1)
PreamDet’: 3(1)15(1)17(1)
PreamEM’: 15(2)17(1)
PreEdgeClock/a: 2(1) 4(1) 5(1)10(1)12(1)13(2)
PreEdgeClock/b: 2(2)12(1)
PreRamClock: 4(1)10(3)12(1)
PreRClk: 15(3)
PreRClock: 6(1)15(2)17(1)
PreRClockEM:15(3)17(1)
PreWR: 12(1)
PreWriteData’: 2(1)12(1)
PreWW: 7(1)
PurgeMode: 2(2) 7(2) 8(1)13(1)
PurgeModeDelayed: 2(1)13(1)
RamClockFeed’:12(1)
RClock: 6(3)15(1)
RData.0’: 4(1) 6(1)
RData.1’: 4(1) 6(1)
RData.2’: 4(1) 6(1)
RData.3’: 4(1) 6(1)
RData.4’: 4(1) 6(1)
RData.5’: 4(1) 6(1)
RData.6’: 4(1) 6(1)
RData.7’: 4(1) 6(1)
RDataParity’: 5(1) 6(2)
ReadData: 2(2) 3(3) 4(1) 5(1) 7(1)
ReadData’: 2(2)
Reset’: 2(1)15(1)
Reseta7: 14(1)17(1)
ResetInput’: 2(1) 3(3) 6(1) 7(2) 8(1)13(1)
ResetOutput: 2(1)13(1)
ResetOutput’: 2(1) 7(1) 8(1) 9(2)11(2)12(2)
Run: 2(1)
SelectInHigh: 4(1) 6(1)
SelectInLow: 4(1) 6(1)
SelectOutHigh:10(1)11(1)
SelectOutLow: 9(1)10(1)11(1)
SendMode: 11(4)12(2)
SendMode’: 11(2)
SendModeDelayed:11(2)
SerialRData: 6(1)15(1)17(1)
SerialRData’: 5(1) 6(2)15(1)17(1)
SerialTData:11(2)14(1)
SKY/a: 1(5) 2(2) 8(2)12(7)13(4)
SKY/b: 2(1) 7(1)10(2)11(4)12(3)13(2)
14(3)15(8)
SKY/c: 2(3) 3(5) 5(2) 6(5) 7(2) 9(2)
11(3)12(1)
SRClock: 1(1)
SRDataEM: 15(2)17(1)
SRDataEM’: 15(2)17(1)
SRDataIn’: 1(1)
SRDataOut’: 1(1)
StartWireRead:11(1)12(1)
TBadCRC: 6(1)
TClk: 14(1)17(1)
TClock: 11(5)15(1)
TClock’: 11(1)14(1)15(1)
TClockEM: 14(1)15(1)
TClockEM’: 14(1)15(1)
TCRCClk: 6(1)17(1)
TData.0’: 10(1)11(1)
TData.1’: 10(1)11(1)
TData.2’: 10(1)11(1)
TData.3’: 10(1)11(1)
TData.4’: 10(1)11(1)
TData.5’: 10(1)11(1)
TData.6’: 10(1)11(1)
TData.7’: 10(1)11(1)
TData0’: 11(2)
TDataParity:11(2)
TDn: 17(2)
Transceiver15V:16(1)
Transmit: 13(2)
Transmit’: 13(2)
TRData: 15(1)
TUp: 17(2)
VCC: 14(5)15(4)16(6)17(2)
VDD: 16(1)
WakeInTime’:13(3)
WakeOutTime’:13(3)
WakeP1’: 13(2)
WakeP2’: 13(2)
WakeP3’: 13(2)
WireRead: 9(1)10(3)12(2)
WireWrite: 4(1) 7(1)
WriteData: 2(1) 9(2)10(2)
WriteIB’: 3(2) 4(1) 5(1)
XData: 14(1)15(1)
XmtData’: 14(1)15(1)
XmtMode’: 11(1)14(1)
XOP: 15(1)