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D0 Tester Reference Manual
This document is for internal Xerox use only.
D0 TESTER Reference Manual
by J.F.Cameron
C.Tseng
November 10, 1977
This manual describes the tester to be used for the firmware development and checkout of the EOD designed D0 processor.
XEROX
INFORMATION TECHNOLOGY GROUP
Electronic Operations Department
Los Angeles / Palo Alto
This document is for internal Xerox use only.
1.0 General: The D0Tester utilizes the Alto computer as the basic test tool which connects with special tester logic thru the Diablo printer interface. This tester logic in combination with the Alto software will provide the following capabilities:
1. A connector which will accept and provide power for a D0 logic module.
2. Logic through which Alto software may set or read the state of any of the I/O pins on the connector.
3. Additional test connections which will allow the above monitor and control functions at internal points on a module or the backplane. These connections will be in the form of both "dip-clips" and clip leads.
4. A test cable which will provide connections from the logic module test connector to a slot in the D0 backplane. All lines will be buffered at the D0 connections and will provide monitoring only. An interlock is provided so that these lines cannot be driven by the tester.
5. A RAM which will simulate the D0 control module EPROMs. This RAM will be loaded from the Alto and will be read into the D0 I MEM when Boot is initiated. Connections to D0 will be made by a cable which plugs directly into the EPROM sockets.
6. Clock control logic which will allow n clocks or instructions to be cycled, where 0 < n < 256 will cause n clocks or instructions to run, n = 0 will stop the clock, and n > 255 will allow the clock to run continuously. Means for stopping the clock by an external signal are provided.
7. A data transfer facility from the Alto to D0. Alto software will load a register in the test logic on a byte basis which may then be read by D0 through its local printer interface.
8. A data transfer facility from D0 to Alto. The D0 local printer interface output lines may be read thru the tester logic by Alto software in "nibbles" (4 bit groups).
9. An attention line from D0 is passed through the tester to the Alto printer interface which may be used by the D0 firmware to indicate the need for data, completion of a subroutine, arrival at a break-point, etc.
10. The tester will contain the necessary logic to allow Alto software to read the content of the EPROM simulator RAM data and address register.
2.0 Alto Commands: The test logic is controlled by the content of Alto memory location UTILOUT (printer interface). For those functions (commands) which require a strobe, the sequence of Alto instructions should be as follows:
UTILOUT ← DATA[01-15]
UTILOUT ← DATA[01-15] v STROBE[00]
UTILOUT ← DATA[01-15]
The six major control groups are:
Group 0 - Pin Control
Group 1 - Clock Control
Group 2 - Load RAM Address
Group 3 - Load RAM Data
Group 4 - Load Data Byte (Alto to D0)
Group 5 - Read Data Nibble (D0 output or internal)
The specific format and bit usage in each of these groups is given in the following paragraphs.
2.1 Pin Control Command: Format for the pin control command is as follows:
Bit 00 - Strobe; required
Bit 01 = 0; defines control group
Bit 02 = 0; defines control group
Bit 03 = 0; defines control group
Bit 04 if = 1, enables drive to pin n
Bit 05 if = 1, causes pin address n to be driven to the state of
command bit 06 if drive is enabled
Bit 06 - pin n address is driven to the state of this bit if drive
is enabled and command bit 05 = 1
Bit 07 if = 1, state of pin address n is placed on UTILIN04;
the state of this pin may then be read at any
time until n is changed and the strobe sequence
for control group 0 issued with bit 07 = 1
Bit 08 - pin address (n), msb
Bit 09 - pin address (n)
Bit 10 - pin address (n)
Bit 11 - pin address (n)
Bit 12 - pin address (n)
Bit 13 - pin address (n)
Bit 14 - pin address (n)
Bit 15 - pin address (n), lsb
The enable functions allows inhibiting of the forced drive of output pins which could cause possible damage to the card under test or to the tester. Note that a pin may be selected for reading, and then be monitored while the state of other pins is changed. See Table 1 for pin addresses with respect to the actual pin on the module under test.
2.2 Clock Control Command: Format for the clock control command is as follows:
Bit 00 - Strobe; required
Bit 01 = 0; defines control group
Bit 02 = 0; defines control group
Bit 03 = 1; defines control group
Bit 04 if = 1, causes D0 to boot
Bit 05 if = 1, causes n clocks to be run if 0 < n < 256;
takes precedence over bit 06
Bit 06 if = 1, causes n instructions to be run if 0 < n < 256
Bit 07 - number n, msb
Bit 08 - number n
Bit 09 - number n
Bit 10 - number n
Bit 11 - number n
Bit 12 - number n
Bit 13 - number n
Bit 14 - number n
Bit 15 - number n, lsb
The clock may be stopped at any time by issuing the strobe sequence with control group 1 and n = 0, or n = 256. The clock may also be stopped by an external positive going TTL level signal applied to pin 122 of tester module A. When not in use for external stop, pin 122 must be grounded.
2.3 Load RAM Address Command: The format for the load RAM address command is as follows:
Bit 00 - Strobe; required
Bit 01 = 0; defines control group
Bit 02 = 1; defines control group
Bit 03 = 0; defines control group
Bit 04 = x; not used by this command
Bit 05 = x; not used by this command
Bit 06 - RAM address, msb
Bit 07 - RAM address
Bit 08 - RAM address
Bit 09 - RAM address
Bit 10 - RAM address
Bit 11 - RAM address
Bit 12 - RAM address
Bit 13 - RAM address
Bit 14 - RAM address
Bit 15 - RAM address, lsb
2.4 Load RAM Data Command: The format for the load RAM data command is as follows:
Bit 00 - Strobe; required
Bit 01 = 0; defines control group
Bit 02 = 1; defines control group
Bit 03 = 1; defines control group
Bit 04 if = 1, data byte in bits 08 thru 15 is loaded into
most significant half of the word addressed
by the RAM address register
Bit 05 if = 1, data byte in bits 08 thru 15 is loaded into
least significant half of the word addressed
by the RAM address register
Bit 06 = x; not used by this command
Bit 07 = x; not used by this command
Bit 08 - RAM data byte, msb
Bit 09 - RAM data byte
Bit 10 - RAM data byte
Bit 11 - RAM data byte
Bit 12 - RAM data byte
Bit 13 - RAM data byte
Bit 14 - RAM data byte
Bit 15 - RAM data byte, lsb
The UTILOUT ← DATA[01-15] v STROBE[00] instruction of the strobe sequence causes the data to be loaded into the RAM. When the second UTILOUT ← DATA[01-15] instruction is issued, if UTILOUT[04] = 1 the RAM address register is incremented by one, making ready to load into the next RAM address. Note that if both bits 04 and 05 are = 1, the data in bits 08 thru 15 are loaded into both halves of the output register during the same strobe sequence.
2.5 Load Data Byte Command: This command sets data into a register which may be read by D0 through its local printer interface. Format for this command is as follows:
Bit 00 - Strobe; required
Bit 01 = 1; defines control group
Bit 02 = 0; defines control group
Bit 03 = 0; defines control group
Bit 04 if = 1, data byte in bits 08 thru 15 is loaded into
most significant half of output register; this
byte drives the D0 printer status output.
Bit 05 if = 1, data byte in bits 08 thru 15 is loaded into
least significant half of output register; this
byte drives the D0 printer data if D0 printer
status input bit 7 is high.
Bit 06 = x; not used by this command
Bit 07 = x; not used by this command
Bit 08 - data, msb
Bit 09 - data
Bit 10 - data
Bit 11 - data
Bit 12 - data
Bit 13 - data
Bit 14 - data
Bit 15 - data, lsb
Note that if both bits 04 and 05 are = 1, the data in bits 08 thru 15 are loaded into both halves of the output register during the same strobe sequence.
2.6 Read Data Nibble Command: The read nibble control group places four bits of data on the Alto printer interface lines, UTILIN00 thru UTILIN03. The strobe sequence is not necessary for this command. The selected nibble of data will remain on the UTILIN lines as long as UTILOUT holds command data with the following format:
Bit 00 = 0; not used by this command
Bit 01 = 1; defines control group
Bit 02 = 0; defines control group
Bit 03 = 1; defines control group
Bit 04 if = 1, data nibble n from D0 local printer interface
will be placed on UTILIN[00-03]; these bytes
are inverted from the D0 output. Nibbles 0 and 1
contain the D0 printer status input, nibbles
3 and 4 contain the D0 printer data.
Bit 05 if = 1, data nibble n of the tester RAM data will
be placed on UTILIN[00-03]
Bit 06 if = 1, data nibble n of the tester RAM address register
will be placed on UTILIN[00-03]
Bit 07 = x; not used by this command
Bit 08 = x; not used by this command
Bit 09 = x; not used by this command
Bit 10 - Turned around on UTILIN[00]; selected by RAM address register, nibble 3
Bit 11 - Turned around on UTILIN[01]; selected by RAM address register, nibble 3
Bit 12 - Turned around on UTILIN[02]; selected by RAM address register, nibble 3
Bit 13 - Turned around on UTILIN[03]; selected by RAM address register, nibble 3
Bit 14 - nibble n, msb
Bit 15 - nibble n, lsb
Bits 14 and 15 specify the nibble to be read, with 00 being the most significant of the possible nibbles available from the data source, i.e., four nibbles from D0, four nibbles of RAM data, and three nibbles of RAM address (nibble 03, when RAM address data is specified, selects command bits [10-13] for turn around test purposes). Only one of the data sources should be specified in any one command, otherwise, a logical or’ing of the data will occur. Additionally, when reading RAM data the D0 clock should be stopped as the RAM chips are selected and could cause possible interference with the running of D0.
3.0 Control Programs: Control of the test logic and display of pin states and other available data is accomplished through Alto software. Retrieval of data from internal registers in D0 is accomplished through the use of Alto software and D0 firmware.
3.1 Alto Software: The Alto software and method of preparing programs for use with the tester are described in memos from C. Thacker to Distribution, dated 3 July 1977, subject D0 Card Testing, and dated 20 October 1977, subject D0 Card Testing II.
3.2 D0 Firmware: To be supplied at a later date.
4.0 Power Supplies and Control: The power supply for the tester logic is separate from those supplying power to the card under test. +5V, -5V, and +12V are available for the card under test and are separately controlled by a switch on the control panel. An interlock is connected to this switch such that the drive to all pins under test is set to the high impedance state whenever power to the card under test is turned off.
Voltage and current monitors for all supplies are provided, as well as indicators on the power supplies. Overvoltage protection is that provided by the supplies themselves.
5.0 Physical Description: The tester logic is housed in a separate enclosure. Connection to the Alto is made by a cable connected to the Alto printer interface. The enclosure contains the tester logic modules, power supplies as described in section 4.0, power control, fans for cooling, and connectors and test cables for the card under test. Connections from the logic modules to the test connectors are made via dip-cable connections. The cables to D0 (EPROM simulator, clock control, and data transfer) are also made to the logic modules thru dip-cable connectors. There are six tester logic modules built on 60 DIP Augat stitch weld cards. The entire enclosure may be placed on a table top alongside an Alto to form a complete test station.
6.0 Documentation: The following files stored in the MAXC EOD account describe the design and operation of the tester:
D0TesterMan.bravo
D0TesterCmdSum.dm
D0TesterBsil.dm
D0TesterCDE.sil
D0TesterFsil.dm
D0TesterGsil.dm
D0TesterBP1.bravo
D0TesterLayout.sil
TABLE 1
MODULE PIN PIN ADDRESS MODULE PIN PIN ADDRESS
UNDER TEST UNDER TEST
002000102064
003001103065
004002104066
005003105067
006004106068
007005107069
008006108070
009007109071
011008111072
012009112073
013010113074
014011114075
015012115076
016013116077
017014117078
018015118079
019016119080
018017121081
022018122082
023019123083
024020124084
025021125085
026022126086
027023127087
028024128088
029025129089
031026131090
032027132091
033028133092
034029134093
035030135094
036031136095
037032137096
038033138097
039034139098
041035141099
042036142100
043037143101
044038144102
045039145103
046040146104
047041147105
048042148106
049043149107
T044 T108
E E
S t S t
T h T h
r r
C u C u
L L
I I
P059 P123
AB.E097060AC.E097124
AB.E098061AC.E098125
AB.E099062AC.E099126
AB.E100063AC.E100127
Continued on next page.
TABLE 1 (continued)
MODULE PIN PIN ADDRESS MODULE PIN PIN ADDRESS
UNDER TEST UNDER TEST
052128152192
053129153193
054130154194
055131155195
056132156196
057133157197
058134158198
059135159199
061136161200
062137162201
063138163202
064139164203
065140165204
066141166205
067142167206
068143168207
069144169208
071145171209
072146172210
073147173211
074148174212
075149175213
076150176214
077151177215
078152178216
079153179217
081154181218
082155182219
083156183220
084157184221
085158185222
086159186223
087160187224
088161188225
089162189226
091163191227
092164192228
093165193229
094166194230
095167195231
096168196232
097169197233
098170198234
099171199235
T172 T236
E E
S t S t
T h T h
r r
C u C u
L L
I I
P183 P251
AD.E097184AE.E097252
AD.E098185AE.E098253
AD.E099186AE.E099254
AD.E100187AE.E100255