//**************************************************************************************
//*** UTVFC2a.TST
//*** Rev.H                                        May 25.1979
//*** Rev.F                                        January 29, 1979
//*** Rev.D2                                      November 28,1978
//*** Rev.B												June29.1978
//*** V. Vysin
//*** TEST 23.4 WAS CHANGED TO LOOK FOR "1"
//*** BY FRANK VEST 8-10-80                                                 
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}

//**************************************************************************************


// test 23 to check the wake-up logic on p.3
let Test23() be
[
   Start()
// SubTest 23.0 to check out the Wake Request path
   Reset()                       // -Allow WU =0

   Switch()             // Allow WU was zero during the Switch
   NClk(1)
   EClock()            // to clock WakeRequest ff
   Compare ("Wake Request ff",{WakeRequest}, 0,"should not set now",1)

   {ODataL} =#2 ;         // Allow WU =1
   {ODataM} =#200;          // 2 to force AAR  load
   ClkCR()                      // loads CR
   ClkStart()                     // loads SAR
   NClk(1)                         // loads AAR with 0
    // In the following,we must write Switch subroutine explicitly,since we want AllowWU =1 during clocking of WakeRequest ff

   {OData3} = #12 ;      // SetCPhase
   WriteHorCont()
   NClk(1)                  // sets SetCPhase

   {OData3} = 2 ;           // Switch only,we must drop setCPhase
   WriteHorCont()           // writes into HeRAM

   NClk(1)                  // sets ControlPhase
   NClk(1)                    // Switch =1 now,SetCPhase=0

   {OData3} = 0 ;        // housekeeping
   WriteHorCont()        // adddress 0 cleared again  

   NClko(2)
//Switch =0,ControlPhase=0,AllowWU=1
   EClock()               // to clock WakeRequest ff
   Compare ("Wake Request ff",{WakeRequest}, 1,"should have set here",2)

   {IOStrobe} =1 ;              // MyTask =1,should have been...
   {IOStrobe} =0 ;              // 
   Compare ("Wake Request ff",{WakeRequest}, 1,"still up here",3)
   EClock()
   Compare ("Wake Request ff", {WakeRequest}, 1,"still up here",4)
   // To prepare now for the next test !
   {ODataM} = #200 ;   //OutD.0 =1 to keep IAR from loading  *
   ClkStart()
   NClk(1)                 // 0 into AAR,AAR left in loading state

   {OData3} = #12 ;      // SetCPhase,PSwitch
   WriteHorCont()
   NClk(1)                  // sets SetCPhase
   NClk(1)                  // sets ControlPhase 

   {OData3} = 2 ;           // Switch only,we must drop setCPhase
   WriteHorCont()           // writes into HeRAM
   NClk(1)                     // Switch =1 now,SetCPhase=0

   {OData3} = 0 ;        // housekeeping
   WriteHorCont()        // adddress 0 cleared again
   NClko(2)
   EClock()
   Compare ("Wake Request ff",{WakeRequest}, 1,"should have set again",5)


  
//Both WakeReq and WakeRequest ff are in good shape
    

//SubTest 1  : to test wake-up logic  on p.3

//{WakeP: WakeP1', WakeP2', WakeP3' }
//{Wake: Wake1, Wake2, Wake3, Wake4}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}

//foo represents the contents of PROM
//	let foo=table [ #17; #47; #207; #7; #33; #63; #223; #23; #112; //#142; #302; #102; #10; #40; #200; #0 ]

//p1 represents the {WakeP} value for phase 1
	let p1=table [#6; #6; #6; #6; #5; #5; #5; #5; #3; #3; #3; #3; #7; #7; #7; #7] 

//p2 represents the {WakeP} value for phase 2
	let p2=table [#6; #5; #3; #7; #6; #5; #3; #7; #6; #5; #3; #7; #6; #5; #3; #7] 

//p3 represents the {Wake} value for phase 2
	let p3=table [ #16; #14; #14; #14; #16; #14; #14; #14; #12; #10; #10; #10; #2; #0; #0; #0]  


    for i=0 to #17 do
    [
       {WakeP}=###;        // just to be sure it is disconnected
       SetCAddr(i)
       {CTask}=i ;      //this will make MyTask'=1
       {Phase1Next'}=0 ;  // WakeRequest =1
      EClock()           //G1,G2,G3 now Phase1(msb),d gate will make dTx'=low &load Transmit =1;Phase1'=0
       Compare("Transmit",{Transmit},1," ff or '63 gate bad",6,i )
       let sb1=p1!i
       let sb2=p2!i
       Compare("WakeP lines", {WakeP}, sb1, "slept over- probably the S32 gate",7,i)
       {Phase1Next'}=1;  //Phase1' still low (c gate closed)
       //Compare("GOTCHA..",{RUN},0," ",101)
       EClock()     // Transmit will stay 1. Phase1' is now high !
       Compare("Transmit",{Transmit},1," ff or '63 gate bad",8,i )
       Compare("Output Wake lines", {WakeP}, sb2, "something wrong with S38 driver",9,i)

        {CTask}=#17-i ;      //this will make MyTask'=0,close d gate
       {Phase1Next'}=0;   // closes c gate
      EClock()               //will make Transmit =0
       Compare("Transmit",{Transmit},0,"shouldn't ",10,i ) 
       //Phase1'=low now

          let sb3=p3!i
          {WakeP1'}=0
          {WakeP2'}=0
          {WakeP3'}=0
          {Phase1Next'}=1
          EClock()           //to clock G3 ph2 into v9 reg
          Compare("Wake lines", {Wake}, sb3, "outa whakes-",11,i)
               //now,since sb3is not equ 17,dTx' will remain high
          EClock()           
          Compare("Transmit",{Transmit},0,"shouldn't ",11,i )
   ]

        // This tested mainly the G123,G23,G3 ; locv9. Now one path in v10 - c gate - and Wake 4 remains untested

    SetCAddr(#17)   ;      //to make G1,G2,G3 =0     
    {CTask}=#17 ;      //this will make MyTask=0... opens d gate

    {Phase1Next'}=0;   //dTx'=0(d)
    EClock()          //will load Transmit=1,Phase1'=0 ,Wake4=1
    Compare("Transmit",{Transmit},1,"-doesn't ",12 )
    {CTask}=#0 ;      //this will make MyTask=1... closes d gate
    {WakeP1'}=1
    {WakeP2'}=1
    {WakeP3'}=1
    {Phase1Next'}=1
    EClock()           //Transmit=1(a),Phase1'=1,C gate causes dTx'=0
    Compare("Transmit",{Transmit},1,"-doesn't ",13)
    {WakeP1'}=0
    {WakeP2'}=0
    {WakeP3'}=0
    EClock()          //will load Transmit=1 (c was 1)
    Compare("Transmit",{Transmit},1,"still ",14)
    {Phase1Next'}=0 ;     //dTx'=1,Phase1' still hi(blocks a)
    EClock()          //will load Transmit=0
    Compare("Transmit",{Transmit},0,"shouldn't ",15)

     {WakeP}=###; 
      SetCAddr(#17) ;   //allimportant;mustrestore MyTask &ICompar      
     Compare("MyTask",{MyTask},1,"Compare went berserk",16)  
     Stop()
]

//the priority logic is in good shape


//**************************************************************************************
//subroutines used for wake-up logic

//SetCAddr(arg)
//to set CAddr=arg
//			where arg=#0-#17
and SetCAddr(arg) be
[
	for caa=0 to 3 do
	[
		let cab=arg & 1
		{SRIn'}=cab
		SRClock()
		arg=arg rshift 1
   ]
]

//******************************************************************************