//D0 Card Tester Program for EtherNet
//Test2A: Output Buffer Test
//R. Garner August 1, 1978  1:03 AM
//R. Crane November 7, 1978  3:24 PM

get "testdefs.d"
get "spgxwtest.d"

//{IData:IData.00,IData.01,IData.02,IData.03,IData.04,IData.05,IData.06,IData.07,IData.08,IData.09,IData.10,IData.11,IData.12,IData.13,IData.14,IData.15}
//{OData:OData.00,OData.01,OData.02,OData.03,OData.04,OData.05,OData.06,OData.07,OData.08,OData.09,OData.10,OData.11,OData.12,OData.13,OData.14,OData.15}
//{CTask:CTask.0,CTask.1,CTask.2,CTask.3}
//{U57A':U57A'.0,U57A'.1,U57A'.2,U57A'.3}
//{U57D:U57D.0,U57D.1,U57D.2,U57D.3}
//{U57Q':U57Q'.0,U57Q'.1,U57Q'.2,U57Q'.3}
//{IAddr:IAddr.0,IAddr.1,IAddr.2,IAddr.3,IAddr.4,IAddr.5,IAddr.6,IAddr.7}
//{TData':TData.0',TData.1',TData.2',TData.3',TData.4',TData.5',TData.6',TData.7'}
//{RamClock:RamClockFeed',RamClockFeed'}
//{EClock:EdgeClockFeed',EdgeClockFeed'}
//{PreRClk:PreRClock,PreRClock}
//{TClk:TClock,TClock',TClock,TClock'}
//{LoadHalfCAddr:SRClock,SRClock,SRDataIn',SRClock,SRClock,SRDataIn',SRClock,SRClock,SRDataIn',SRClock,SRClock,SRDataIn'}


let Test2A(auto,Size,TChar,enable) be
[
if (auto eq false)  do
	[
	let TChar,Size=nil,nil
	Wss(D,"*nTest2:EN Output Test; How many words should be sent(0-f=15)(>=c=>underrun)?")
	while Endofs(keys) do []
	let char=Gets(keys)
	switchon char into
	[
		case	$1:	Size=1;	endcase
		case	$2:	Size=2;	endcase
		case	$3:	Size=3;	endcase
		case	$4:	Size=4;	endcase
		case	$5:	Size=5;	endcase
		case	$6:	Size=6;	endcase
		case	$7:	Size=7;	endcase
		case	$8:	Size=8;	endcase
		case	$9:	Size=9;	endcase
		case	$a:	Size=10;	endcase
		case	$b:	Size=11;	endcase
		case	$c:	Size=12;	endcase
		case	$d:	Size=13;	endcase
		case	$e:	Size=14;	endcase
		case	$f:	Size=15;	endcase
		default:	return
	]
	Wss(D,"*nDo you want to set Bad Status?(y)(Size<=b)")
	while Endofs(keys) do []
	let TChar=Gets(keys)
	]
	let S,i,TDataByte = nil,nil,nil
	{Run}=0
	{LoadHalfCAddr}=ICA;	//InCAddr=14B
	{LoadHalfCAddr}=OCA;	//OutCAddr=5B
	{CTask}=5B
	{IValid'}=1
	{MC2StartXport}=0
	{OFault'}=1
	{Phase1Next'}=1;	//so no transmit
	{EdgeClockFeed'}=1
	{RamClockFeed'}=1
	Wss(D,"*nTest2a: Load OB")
	if (enable)   do  Wss(D,"*nDisconnect pins 1 & 2 of chip U54 (b11) from rest of circuit for test.")
	Position(enable,"B(16)","U57","B(16)","f16");	//Low 4-bit Ram
	Position(enable,"C(20)","U47","C(20)","f14");	//OutSR
	Position(enable,"D(16)","U7","D(16)","c10");	//Tclock
	Position(enable,"E=PlatformClip A","Z54Z","E=PlatformClip A","e5")
	Position(enable,"E=PlatformClip B","U84","E=PlatformClip B","b15")
	Position(enable,"E=PlatformClip C","U80","E=PlatformClip C","f13")
	{SRData}=0
	{SRData'}=1
	{Carrier}=1
	{PreamDet'}=1
	{TClock}=1
	{TClock'}=0
	{PreRClock}=0
	{Collision}=0
	{PreRClk}=PreRclick
	{TClk}=Tclick; 	//enough to clear OutSRC,PacketOutMode
	{TClk}=Tclick
	{TClk}=Tclick
	{TClk}=Tclick
	{EClock}=Eclick;	//enough to clear out a possible Wire Read
	{Phase1Next'}=0;	//so no transmit, must go to 0 for one cycle to initialize.
	{EClock}=Eclick
	{Phase1Next'}=1;	//so no transmit
	{EClock}=Eclick
	{Run}=1
//enable output
	LoadState(120B,102B)
//output first data word & leave WriteData set
	{IAddr}=123B
	{AdvPipe'}=0
	{EClock}=Eclick
	{MC2StartXport}=1
	{EClock}=Eclick
	{MC2StartXport}=0
	{OData}=401B;	//first data word
	{OData.16}=1
	{OValid'}=0
	{AdvPipe'}=1
	{EClock}=Eclick
     {RamClockFeed'}=0
	Compare({U57CS'},0,"U57 (f16)CS'");	//selected by WireWrite
     {RamClockFeed'}=1
//	Compare({OutDiffNE0},0,"OutDiffNE0'")
//load the output buffer
	for i = 1 to Size do
	[
		Compare({U57A'},not(i-1) & 17B,"OBAddr")
		if i ne Size & TChar ne $y then Compare({U57D},i & 17B,"OutData[12..15]")
//		Compare({OutDiffLE11},(i-1 le 11) & 1,"OutDiffLE11")
		{RamClock}=Ramclick;	//Write Ram
		if i ne Size & TChar ne $y then Compare({U57Q'},not(i) & 17B,"U57 (f16)Q'")
		S=((i+1) lshift 8) % (i+1)
		{OData.16}=not(S<<w.b12 xor S<<w.b13 xor S<<w.b14 xor S<<w.b15 xor S<<w.b4 xor S<<w.b5 xor S<<w.b6 xor S<<w.b7)
		if (TChar eq $y) & (i+1 ge Size) then S=S xor 1;	//reverse bit15 for bad parity
		{OData}=S
		{EClock}=Eclick;	//Incr DOP & Load PreOB
		if i+1 ge Size then {OValid'}=1
//		Compare({OutDiffNE0},1,"OutDiffNE0'")
	]
//read the output buffer & send
	Wss(D,"*nTest 2b: Give the bits to the wire")
//Set OutEOP if neccessary
	if Size le 11 then LoadState(120B,106B)
	Compare({U57A'},17B,"U57 (f16)A'");	//WOP should be selected
//Set PacketOutMode
	{EClock}=Eclick;	//Set OutDiffLE11
	{Carrier}=0
	Compare({PacketOutMode},0,"PacketOutMode")
	{TClk}=Tclick
	{TClk}=Tclick
	{TClk}=Tclick
	Compare({PacketOutMode},1,"PacketOutMode")
	Compare({U57CS'},0,"U57 (f16)CS'")
	Compare({LoadOutSR},0,"LoadOutSR")
//Clock away garbage word
	for i = 1 to 7 do {TClk}=Tclick
	Compare({LoadOutSR},1,"LoadOutSR")
//Garbage-Load OutSR & cause WireRead
	{TClk}=Tclick
	Compare({U57CS'},1,"U57 (f16)CS'")
	Compare({LoadOutSR},0,"LoadOutSR")
	{EClock}=Eclick
	{EClock}=Eclick
	{EClock}=Eclick;	//load PostOB with first high byte
	Compare({TData'},not(1) & 377B,"TData'")
//Prepare to Load OutSR with first high byte
	for i = 1 to 7 do {TClk}=Tclick
	Compare({SendMode},0,"SendMode")
//Transmit Words
	for i = 1 to Size do
	[
		for j = 0 to 1 do
		[
			//Load OutSR with High/Low Byte
			Compare({LoadOutSR},1,"LoadOutSR")
			{TClk}=Tclick
			Compare({SendMode},1,"SendMode")
			TDataByte={TData'}
			test i eq Size & j eq 1 & TChar eq $y
				ifso Compare(TDataByte xor 1,not(i) & 377B,"TData'")
				ifnot Compare(TDataByte,not(i) & 377B,"TData'")
			Compare({U57CS'},j & 1,"U57 (f16)CS'")
			if i ne Size & j ne 1 then Compare({U57Q'},not(i+j) & 17B,"U57 (f16)Q'")
			//Transmit High/Low Byte
			for k = 1 to 7 do 
			[
				if k eq 5 then
				[	
					//do a WireRead
					{EClock}=Eclick
					{EClock}=Eclick;	//set WireRead
					{EClock}=Eclick;	//PostOB _ LowByte,Incr WOP, Reset WR
					Compare({U57A'},not(i) & 17B,"U57 (f16)A'")
				]
				{TClk}=Tclick
				Compare({TData0'},(TDataByte rshift (7-k)) & 1,"TData0'")
				if TChar ne $y then Compare({BadParity},0,"BadParity")
			]
		]
	]
//Program is broken here.  Remainder of test 2 is in Test2B.
Test2B(TChar,Size,S,enable)
]