//****************************************************************************** //*** UTVFC6c.TST //*** Rev. H May 29.1979 //*** Rev. F February 13,1979 //*** V. Vysin //************************************************************************************** //************************************************************************************** //To include the following definition files in the compilation get "tester.d" get "UTVFC.d" //************************************************************************************** //{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07} //{ODataL: Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15} //{OData0: Odata.00, Odata.01, Odata.02, Odata.03} //{OData1: Odata.04, Odata.05, Odata.06, Odata.07} //{OData2: Odata.08, Odata.09, Odata.10, Odata.11} //{OData3: Odata.12, Odata.13, Odata.14, Odata.15} //{T0: T0D0, T0D1, T0D2, T0D3} //{T1: T1D0, T1D1, T1D2, T1D3} //{T2: T2D0, T2D1, T2D2, T2D3} //{T3: T3D0, T3D1, T3D2, T3D3} //{CTask: CTask.0, CTask.1, CTask.2, CTask.3} let Test64() be [ Start(1) let i=2 S3: unless i ls 0 do [ Switch() // PBlank=1 NClko(#160)// PBlank=1,both BckGnds are high NClk(1) // BlankTerm {ODataM}=7 {ODataL}=#374+i ClkCur() NClk(1) // loaded addr reg;CoShift =1 Switch() NClko(#140) // PBlank=0,both BckGnds are high // makes DisablCurs'=high(disables loading)releases CursMem outpt NClk(1) // loads u54,u51(first nibble from??line) //does not increment counter,makes BlankTerm=0 NClk(1)//loads u54,u51(firstnibblefrom??line) loads first //line address, loads u40(firstnibble from x)doesn't increm.cntr NClk(1) // loads u54,u51 w.first nibble of selected //line,loads u40(first nibble from x),increments counter for n=0 to 7 do [ if i eq 2 do [ test n eq 0 ifso [ Compare("Register T0",{T0}, 6,"is acting up ", 5,n) Compare("Register T0",{T1}, 6,"is acting up ", 6,n) ] ifnot [ Compare("Register T0",{T0}, 14*(1-n rem 2) +1*n rem 2,"is acting up ",7,n) Compare("Register T0",{T1}, 14*(1-n rem 2) +1*n rem 2,"is acting up ",8,n) ] ] if i eq 1 do [ test n eq 0 ifso [ Compare("Register T0",{T0}, 3,"is acting up ", 9,n) Compare("Register T0",{T1}, 3,"is acting up",10,n) ] ifnot [ Compare("Register T0",{T0}, 15*(1-n rem 2) , "is acting up ",11,n) Compare("Register T0",{T1}, 15*(1-n rem 2) , "is acting up ",12,n) ] ] if i eq 0 do [ test n eq 0 ifso [ Compare("Register T0",{T0},1,"is acting up ", 13,n) Compare("Register T0",{T1},1,"is acting up ", 14,n) ] ifnot [ Compare("Register T0",{T0}, 7*(1-n rem 2) +8*n rem 2,"is acting up ",15,n) Compare("Register T0",{T1}, 7*(1-n rem 2) +8*n rem 2,"is acting up ", 16,n) ] ] NClk(1) // increments ] i=i-1 goto S3 ] // this absolves the mod 4 shifter and the whole cussor hardware // we now clear the cursor memory for a=0 to 31 do [ {ODataM}= 3+8*a for b=0 to 7 do [ {ODataL} = 4*b +3 ClkCur() NClk(1) {OData3}=0 CurWri() ] ] Stop() ]