//**************************************************************************************
//*** UTVFC4a.TST
//*** Rev.H                                               May 30 1979
//*** Rev.F                                                February 6,1979
//*** Rev.B										August 4.1978         
//*** V. Vysin                                             
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{OData0: Odata.00, Odata.01, Odata.02, Odata.03}
//{OData1: Odata.04, Odata.05, Odata.06, Odata.07}
//{OData2: Odata.08, Odata.09, Odata.10, Odata.11}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{T0: T0D0, T0D1, T0D2, T0D3}
//{T1: T1D0, T1D1, T1D2, T1D3}
//{T2: T2D0, T2D1, T2D2, T2D3}
//{T3: T3D0, T3D1, T3D2, T3D3}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}


let Test42() be
[
   Start()
   {CTask}=#0 
   SetCAddr(#17) ;   //allimportant;mustrestore MyTask &ICompar
   Compare("MyTask",{MyTask},1,"no chance ",1)
   
   let pat = table [ #2; #4; #10; #1 ]
   LoadIAR(0)

//WRITING
//if OAddr.6,OAddr.7 =#1, then
//Terminal 1...byte 0 goes to EB1
//Terminal 0...byte 1 goes to EB1
//Terminal 3...byte 2 goes to EB1
//Terminal 2...byte 3 goes to EB1
   OddLine()                  // to write into even buffer
   for j =0 to 63 do
   [
      let v =j rem 4
      {OData0}=#0
      {OData1}=pat!v
      {OData2}=#0
      {OData3}=#0
      WriteBuf(0)         //writes into terminal 0 ; also includes EClock which loads ODR
   ]
   LoadIAR(0)
   for j =0 to 63 do          
   [
      let v =( j +1 ) rem 4
      {OData0}=pat!v
      {OData1}=#0
      {OData2}=#0
      {OData3}=#0
      WriteBuf(1)         // writes into terminal 1
   ]
   LoadIAR(0)
   for j =0 to 63 do
   [
      let v =( j +2 ) rem 4
      {OData0}=#0  
      {OData1}=#0
      {OData2}=#0
      {OData3}=pat!v
      WriteBuf(2)         // writes into terminal 2
   ]
   LoadIAR(0)
   for j =0 to 63 do
   [
      let v =( j +3 ) rem 4
      {OData0}=#0
      {OData1}=#0
      {OData2}=pat!v
      {OData3}=#0    
      WriteBuf(3)         // writes into terminal 3
   ]
   Compare("MyTask",{MyTask},1,"no chance ",2)
//READING
//First byte from EB1 comes from terminal T1
//Second byte from EB1 comes from terminal T0
//Third byte from EB1 comes from terminal T3
//Fourth byte from EB1 comes from terminal T2

   //EvenLine()               // to read the even buffer
   Switch()
   NClko(#160)     //replaces EvenLine();we don't need the if condition here (we put it in OddLine last time),also we got to assure that both BlackBgd's are hi (SendControl is low on u37 gates!!)AND PBlank=1 to keep DisablCurs'=0 to close both cursors
   LoadAAR(0)
   NClk(1)                    //to load T2 and T3 ; increments AAR
   for j =0 to 63 do
   [
      let v =( j +1 ) rem 4
      Compare("Terminal 2 output",{T2} ,#00," extra ones ",1,j)
      Compare("Terminal 3 output",{T3} ,#00," extra ones ",2,j)
      NClk(1)      // to load T0 and T1 ; increments AAR,loads next T2,T3
      Compare("Terminal 0 output",{T0} ,#00," extra ones ",3,j) 
      Compare("Terminal 1 output",{T1} ,pat!v,"jecch...",4,j) 

      let v =j rem 4
      Compare("Terminal 2 output",{T2} ,#00," extra ones ",5,j)
      Compare("Terminal 3 output",{T3} ,#00," extra ones ",6,j)
      NClk(1)      // to load T0 and T1 ; increments AAR,loads next T2,T3
      Compare("Terminal 0 output",{T0},pat!v,"jecch... ",7,j)
      Compare("Terminal 1 output",{T1} ,#00," extra ones  ",8,j)
 
      let v =( j +3 ) rem 4
      Compare("Terminal 2 output",{T2} ,#00," extra ones ",9,j)
      Compare("Terminal 3 output",{T3} ,pat!v,"jecch... ",10,j)
      NClk(1)      // to load T0 and T1 ; increments AAR,loads next T2,T3

      Compare("Terminal 0 output",{T0} ,#00," extra ones ",11,j)
      Compare("Terminal 1 output",{T1} ,#00," extra ones ",12,j) 
 
      let v =( j +2 ) rem 4
      Compare("Terminal 2 output",{T2} ,pat!v,"jecch...",13,j) 
      Compare("Terminal 3 output",{T3} ,#00," extra ones ",14,j) 
      NClk(1)      // to load T0 and T1 ; increments AAR,loads next T2,T3
      Compare("Terminal 0 output",{T0} ,#00,"  extra ones  ",15,j)
      Compare("Terminal 1 output",{T1} ,#00," extra ones ",16,j)
   ]

// In this test,all nonzero data were written into one particular chip, and all its 4 channels
// were exercised with ones and zeros,aand all locations were used.
// This test therefore
// absolves chip in position u43 of all sins


   Stop()
]

and SetCAddr(arg) be
[
	for caa=0 to 3 do
	[
		let cab=arg & 1
		{SRIn'}=cab
		SRClock()
		arg=arg rshift 1
   ]
]