//**************************************************************************************
//UTVFCa.TST
//*** Rev.H May30,1979
//***Rev. B June 19.1978
//V.Vysin
//Main Test Program and Subroutines for UTVFC Controller Module
//**************************************************************************************
//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"
//**************************************************************************************
//To define bus structure
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}
//{IAddr: Iaddr.0, Iaddr.1, Iaddr.2, Iaddr.3, Iaddr.4, Iaddr.5, Iaddr.6, Iaddr.7}
//{IDataM: Idata.00, Idata.01, Idata.02, Idata.03, Idata.04, Idata.05, Idata.06, Idata.07}
//{IDataL: Idata.08, Idata.09, Idata.10, Idata.11, Idata.12, Idata.13, Idata.14, Idata.15}
//{IData0: Idata.00, Idata.01, Idata.02, Idata.03}
//{IData1: Idata.04, Idata.05, Idata.06, Idata.07}
//{IData2: Idata.08, Idata.09, Idata.10, Idata.11}
//{IData3: Idata.12, Idata.13, Idata.14, Idata.15}
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL: Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData0: Odata.00, Odata.01, Odata.02, Odata.03}
//{OData1: Odata.04, Odata.05, Odata.06, Odata.07}
//{OData2: Odata.08, Odata.09, Odata.10, Odata.11}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{Clocks: ClkCR', ClkStart', ClkIAR', WriteHorCont', WriteOddBuf', WriteEvenBuf'}
//{WakeP' : WakeP1', WakeP2', WakeP3'}
//**************************************************************************************
//Clocking routines defined on p. 5
let RClock() be
[
{RamClockFeed'}=0 ; //RamClkFeed' is normally high
{RamClockFeed'}=1
]
and EClock() be
[
{EdgeClockFeed'}=0 ; //EdgeClkFeed' is normally high
{EdgeClockFeed'}=1
]
and Clocks() be
[
RClock()
EClock()
]
and SetOaddr(g) be
[
{IAddr} =g
{AdvancePipe'} =0
EClock()
{AdvancePipe'} =1
{MC2StartXport} =1
EClock()
{MC2StartXport} =0
]
and InputSequ() be
[
{Advance Pipe'}=0
EClock() //OCompare should become 1
{Advance Pipe'}=1
{MC2StartXport}=1
EClock() //OCompr =1
{MC2StartXport}=0
]
and NClk(k;numargs na) be
[
DefaultArgs(lv na, -1, 0)
unless k eq 0 do
[
{ODataL} =#1 ; //OutD.15 to reset Gray Counter,Allow WU=0
SetOaddr(0) //to prepare ClkCR
{OValid'} =0
EClock() //first after OValid' sets OMeF,loads outD.15
{ODataL} =#200; //OutD.08 to enable clocking of NClk,
EClock() //first CR loads CR ,resets NClk,loads OutD.8
for i=1 to 4*(k-1) do
[
EClock()
]
EClock() // first CR into NClk
EClock()
EClock()
{OValid'} =1
{ODataL} =0 ; //0 is the final contents of Cont.Reg
EClock() //last ClkCR,also resets OMeF,removes OutD.8
]
]
and NClko(cr) be
[
{ODataL} =#1 ; //OutD.15 to reset Gray Counter,Allow WU =0
SetOaddr(0) //to prepare ClkCR
{OValid'} =0
EClock() //first after OValid' sets OMeF,loads OutD.15
{ODataL} =#200+cr; //OutD.08 to enable clocking of NClk,cr is the (even) contents of Control Reg. during the Nclk
EClock() //first CR loads CR ,resets NClk,loads OutD.8
EClock() // first into NClk
EClock()
EClock()
{OValid'} =1
{ODataL} =cr
EClock() //last ClkCR,also resets OMeF ,removes OutD.8
]
and SRClock() be
[
{SRClock} = 0 ; //SRClock is normally high
{SRClock} = 1
]
and Reset() be
[
{RUN} =0 ; //Run is normally high for Controller in operation
{RUN} =1 ; //will make a negative pulse in Rst'
]
and ClkCR() be
[
SetOaddr(0)
{OValid'} =0
EClock() //sets OMeF since OCompr=1 from prev.tests
{OValid'} =1
EClock() //this makes the ClkCR' and resets OMeF
]
and ClkStart() be
[
SetOaddr(1)
{OValid'} =0
EClock() //sets OMeF since OCompr=1 from prev.tests
{OValid'} =1
EClock() //this makes the ClkStart' and resets OMeF
]
and ClkIAR() be
[
SetOaddr(3)
{OValid'} =0
EClock() //sets OMeF since OCompr=1 from prev.tests
{OValid'} =1
EClock() //this makes the ClkIAR' and resets OMeF
]
and ClkCur() be
[
SetOaddr(4)
{OValid'} = 0
EClock() // sets OMeF
{OValid'} = 1
EClock() // makes the pulse,resets OMeF
SetOaddr(5); // the other one too
{OValid'} = 0
EClock() // sets OMeF
{OValid'} = 1
EClock() // makes the pulse,resets OMeF
]
and CurWri() be
[
SetOaddr(6)
{OValid'} = 0
EClock() // sets OMeF
RClock() // the write pulse proper
{OValid'} = 1
EClock() // resets OMeF
SetOaddr(7); // the other one too
{OValid'} = 0
EClock() // sets OMeF
RClock() // the write pulse proper
{OValid'} = 1
EClock() // resets OMeF
]
and WriteHorCont() be
[
SetOaddr(2)
{OValid'} =0
EClock() //sets OMeF since OCompr=1 from prev.tests
{OValid'} =1
RClock() //this makes the WriteHorCont' pulse
EClock() //this resets OMeF
]
and WriteBuf(i) be
[
//EvenLine() //cant be here,would destroy set OData!
//OddLine() //cant be here,would destroy set OData!
SetOaddr(#10 + i)
{OValid'} =0
EClock() //sets OMeF since OCompr=1 from prev.tests
{OValid'} =1
RClock() //this makes the WriteHorCont' pulse
EClock() //this generates ClkIAR' and resets OMeF
]
and WriteAll() be
[
WriteBuf(0)
WriteBuf(1)
WriteBuf(2)
WriteBuf(3)
]
and XeroData() be
[
{ODataL} = 0
{ODataM} =0
]
and EvenLine() be
[
let eli={EvenLine}
if eli eq 0 do
[
Switch()
NClk(1)
]
]
and OddLine() be
[
let eli={EvenLine}
if eli eq 1 do
[
Switch()
NClk(1)
]
]
and Switch() be
[
{ODataM} = #200 ; //OutD.0 =1 to keep IAR from loading
ClkStart()
NClk(1) // 0 into AAR,AAR left in loading state
{OData3} = #12 ; // SetCPhase,PSwitch
WriteHorCont()
NClk(1) // sets SetCPhase
NClk(1) // sets ControlPhase
{OData3} = 2 ; // Switch only,we must drop setCPhase
WriteHorCont() // writes into HeRAM
NClk(1) // Switch =1 now,SetCPhase=0
{OData3} = 0 ; // housekeeping
WriteHorCont() // adddress 0 cleared again
// M U S T be followed by a NClk,which will put Switch =0,ControlPhase=0
]
and HSpulse() be
[
{ODataM} = #200 ; //OutD.0 =1 to keep IAR from loading
ClkStart()
NClk(1) // 0 into AAR;AAR left in loading state
{OData3} = #16 ; // PSwitch=1,PHS=1,SetCPhase=1
WriteHorCont()
NClk(1) // sets SetCPhase;PHS,PSwitch=1
NClk(1) // sets ControlPhase
NClk(1) // sets HS =1, Switch =1
{OData3} = 0 ; // housekeeping
WriteHorCont() // adddress 0 cleared again
// M U S T be followed by a NClk,which will put HS=0, Switch=0, ControlPhase=0
]
and MLpulse() be
[
{ODataM} = #200 ; //OutD.0 =1 to keep IAR from loading
ClkStart()
NClk(1) // 0 into AAR;AAR left in loading state
{OData3} = #1; // ML =1
WriteHorCont()
NClk(1) // sets ML=1
{OData3} = 0 ; // housekeeping
WriteHorCont() // adddress 0 cleared again
// M U S T be followed by a NClk,which will put ML=0
]
and LoadAAR(a) be
[
{ODataM} = #200 + a ; //a limited to 6 bits-starting address
ClkStart()
NClk(1)
{ODataM} = #300 ; // enables counting by Nclk
ClkStart()
]
and LoadIAR(a) be
[
{ODataM} = #100 + a ; //a limited to 6 bits-starting address
ClkStart()
ClkIAR()
{ODataM} = #300 ; // enables counting by Nclk
ClkStart()
]
and PrepareTSR() be
[
{IValid'} = 0
EClock() // sets IMeF
{IAddr} = 4
EClock() // loads IReg
{IAddr} = 0; // enables shifting now
]
// EClock(n) now must follow .Without any pulse,output =VS
and EndTSR() be
[
{IValid'} = 1
EClock() // resets IMeF
]
and SetIMeF() be
[
{IValid'}=0
EClock()
]
and SetOMeF() be
[
{OValid'}=0
EClock()
]
and ResetIMeF() be
[
{IValid'}=1
EClock()
]
and ResetOMeF() be
[
{OValid'}=1
EClock()
]
and SetControlPhase() be
[
{ODataM} =#200
ClkStart()
NClk(1)
{OData3} =#10
WriteHorCont()
NClk(1)
NClk(1)
{OData3} = 0
WriteHorCont()
NClk(1)
]
//Left Cycle-shift routine
and LCyc(wrd,amount)= valof
[
resultis((wrd lshift amount) % (wrd rshift (16-amount)))
]
//Odd-parity checking routine
and Parity(x) = valof
[
let parity = 0
for i = 0 to 15 do
[
parity = parity+x ; //"+" is faster than "XOR"
x = x rshift 1
]
resultis (parity & 1)
]