//**************************************************************************************
//*** UTVFC3a.TST
//*** Rev.H                                                  May 25.1979
//*** Rev.F                                                 February 2.1979
//*** Rev.B														           ***
//*** V. Vysin                                             August 4.1978
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{Start:  Start.0, Start.1, Start.2, Start.3, Start.4, Start.5}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}

//Now we can start checking VS. 

let Test34() be
[
   Start()

    SetBusValue(4,29,93,30,94,#0 )
   SetCAddr(#17) ;   //allimportant;mustrestore MyTask &ICompar      
   

   Reset()         //PreVS =0 , OddField =0
   MLpulse()
   NClko(0)

   PrepareTSR()
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should have been xero",1)
   EndTSR()

   TryHS(#10 )     //PreVS=1,EvenField
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should still have been xero",2)
   FlipwML(#10)
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should have been one",3)
   Recheck(#10)
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should still have been one",4)
   EndTSR()

   TryHS(#0)       //PreVS=0,EvenField
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should still have been one",5)
   FlipwML(#0)
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should have been zero",6)
   Recheck(#0)
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should still have been zero",7)
   EndTSR()
 

   TryML(#14)       //PreVS=1,OddField
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should still have been zero",8)
   FlipwHS(#14)
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should have been one",9)
   Recheck(#14)
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should still have been one",10)
   EndTSR()

 
   TryML(#4)       //PreVS=0,OddField
   Compare("Idata.16",GetPinValue(106), 1,"VS bit, o-o ,it should still have been one",11)
   FlipwHS(#4)
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should have been zero",12)
   Recheck(#4)
   Compare("Idata.16",GetPinValue(106), 0,"VS bit, o-o ,it should still have been zero",13)
   EndTSR()
   Stop()
]

and SetCAddr(arg) be
[
	for caa=0 to 3 do
	[
		let cab=arg & 1
		 SetPinValue(31,cab)
		SRClock()
		arg=arg rshift 1
   ]
]

and TryHS(cr) be
[
   Switch()
   NClko(cr)
   HSpulse()       //the wrong pulse,just trying to confuse it
   NClko(cr)          
   PrepareTSR()
]

and TryML(cr) be
[
   Switch()
   NClko(cr)
   MLpulse()           //the wrong pulse,just trying to confuse it
   NClko(cr)
   PrepareTSR()
]

and FlipwHS(cr) be
[
   EndTSR()
   HSpulse()    //in OddField this is the right one
   NClko(cr)
   PrepareTSR()
]

and FlipwML(cr) be
[
   EndTSR()
   MLpulse()    //in EvenField this is the right one
   NClko(cr)
   PrepareTSR()
]

and Recheck(cr) be
[
   EndTSR()
   MLpulse()
   NClko(cr)
   HSpulse()        // how sneaky, am I an old Meany
   NClko(cr)
   PrepareTSR()
]

//VS ff is declared A-OK

//Lets now quickly check on SendControl logic

and Test35() be
[
   Start()
   NClk(2)         // to clear SendControl ff
   Compare("SendControl",GetPinValue(55),0,"oops ",1)
   SetVS()      // will be in EvenField so that HS is inactivated
   NClk(1)       //for ExtraNibTime to go low
   NClk(1)       //to clock SendControl
   Compare("SendControl",GetPinValue(55),1,"oops ",2)

   ResetVS()
   NClk(1)         //ExtraNibTime
   Compare("SendControl",GetPinValue(55),1,"oops ",3)
   NClk(1)       //to clock SendControl
   Compare("SendControl",GetPinValue(55),0,"oops ",4)   ;//this was by VS
   // what follows now is an explicit Switch subroutine,with some imbedded tests
    SetBusValue(8,167,165,164,163,162,159,156,155,#200)
   ClkStart()
   NClk(1)
    SetBusValue(4,135,134,133,129,#12 );      // SetCPhase,PSwitch
   WriteHorCont()
   NClk(1)                  // sets SetCPhase
   NClk(1)                  // sets ControlPhase 

    SetBusValue(4,135,134,133,129,#6 );     // Switch+HS only,we must drop setCPhase
   WriteHorCont()           // writes into HeRAM
   NClk(1)                     // Switch =1 ,HS=1 now,SetCPhase=0
   Compare("SendControl",GetPinValue(55),0,"oops ",5) ;    // byHS
    SetBusValue(4,135,134,133,129,0  );
   WriteHorCont()
   NClk(1)   //makesHS=0,Switch=0,ControlPhase=0                         
  //SendControl=1,ExNibTime=0
   Compare("SendControl",GetPinValue(55),1,"o-o ",6)
   NClk(1)    //  makes ExtraNibTime =1                         
   Compare("SendControl",GetPinValue(55),1,"o-o ",7)
   NClk(1)                           
   Compare("SendControl",GetPinValue(55),0,"o-o ",8)
  
//Gee, all's well ! Swell !

   Stop()
]
and SetVS() be
[
   Switch()
   NClko(8)        // PreO,AllowWU =0,PreVS=1
   MLpulse()
   NClk(1)
]

and ResetVS() be
[
   Reset()                  // PreO,PreVS =0
   MLpulse()
   NClk(1)
]


//UNKNOWN SIGNALS REQUIRED: