//**************************************************************************************
//*** UTVFC3.TST
//*** Rev.H                                             May 25.1979
//*** Rev.F                                             January 30.1979
//***Rev.D2                                            November 29,1978
//*** Rev.B													 August 4.1978
//*** V. Vysin                                             
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{Start:  Start.0, Start.1, Start.2, Start.3, Start.4, Start.5}
//{Clocks: ClkCR', ClkStart', ClkIAR', WriteHorCont', WriteOddBuf', WriteEvenBuf'}

//**************************************************************************************

// Checking out the Hor.Control RAM ,SetCPhase  bit
let Test31() be
[
   Start()
   for a = 0 to 63 do
   [
      LoadAAR(a)          
      for k = 0 to 3 do
      [
         NClk(k)                //increments AAR in 2 nonloadable lsb
         {OData3} = #10
         WriteHorCont()
         NClk(1)               //first to load v1
         NClk(1)               //second to clock ContPh ff
         Compare("I sakra ControlPhase",{ControlPhase},1,"tenhle flip-flop je v prdeli ",1,k)

         LoadAAR(a)          
         NClk(k)            //restores old address
         {OData3} = 0
         WriteHorCont()      // restores 0 after test
         Switch()            //resets ControlPhase,also reloads AAR
         NClk(1)
         Compare("Ssukin syn ContPh",{ControlPhase},0,"chujovaja jachejka nerabotaet job tvoju matj",2,k)
      ]
   ]
   //We shall now test the v1 switch..

   {ODataM} = #200 ;    // AAR load
   EClock()
   ClkStart()
   NClk(1)

   {OData3} = #17
   WriteHorCont()
   NClk(1)              
   PrepareTSR()
   EClock()     // EvenField
   EClock()      //ML
   Compare(" Idata.16",{Idata.16},1,",ML bit,memory faulty? ",3)
   EClock()
   Compare("Idata.16",{Idata.16},0,"Switch,o-o ",4)
   EClock()
   Compare("Idata.16",{Idata.16},0,"HS, o-o ",5)
   EClock()
   Compare(" Idata.16",{Idata.16},0,",ControlPhase, memory faulty? ", 6)
   EndTSR()

   NClk(1)
   Compare("ControlPhase ",{ControlPhase},1," ",7)
   NClk(1)                    // to load from the other input
   PrepareTSR()
   EClock()
   EClock()
   Compare("ML,Idata.16 ",{Idata.16},1,"now,something's wrong ",8 )
   EClock()
   Compare("Switch,Idata.16 ",{Idata.16},1,",memory faulty?  ",9)
   EClock()
   Compare("HS,Idata.16 ",{Idata.16},1,",memory faulty?  ",10)
   EClock()
   Compare("ControlPhase,Idata.16 ",{Idata.16},1,"now,something's wrong  ",11)
   EndTSR()
   //Here we are leaving the ControlPhase up for the following test  of the other three bits
        
   Stop()
]

//**************************************************************************************

// to test Hor.Cont. RAM, HS, Switch and ML  bit
and Test32() be
[
   Start()
   for a = 0 to 63 do
   [
      LoadAAR(a)
      for b = 0 to 3 do
      [
         NClk(b)          //increments the unloadable 2 lsb of AAR
         let c=1
         unless c gr 4 do ;//does not test all combinations,butallbits
         [
            {OData3} = c + 8 ;     //SetCPh bit blocks Switch
            WriteHorCont()
            NClk(1)
            PrepareTSR()
            EClock()
            EClock()
            Compare("ML,Idata.16",{Idata.16}, c & #1,"bit in memory? ",1,c)
            EClock()
            Compare("Switch,Idata.16 ",{Idata.16},(c rshift 1) & #1,"bit in memory? ",2,c)
            EClock()
            Compare("HS,Idata.16 ",{Idata.16}, (c rshift 2) & #1,"bit in memory? ",3,c)
            EClock()
            Compare("ControlPhase,Idata.16",{Idata.16},1,"bit in memory? ",4,c)
            EndTSR()
            NClk(1)
           Compare("Basamateremtete ControlPhase",{ControlPhase},1,"nemtudum magyarum,again!",5,c)
            LoadAAR(a)  //insert the original address
            NClk(b)        // address mod 4
            {OData3} = 0   
            WriteHorCont()// clear before going to the next  address
            c=2*c
         ]
     ]
   ]          
   Stop()
]
//Now we shall keep in memory that HorCont RAM is in memorably good shape
//**************************************************************************************


and Test33() be
[
   Start()
//SubTest 31.0

// to test EvenLine ff
 
   test {EvenLine} eq 1
   ifso
   [
      Switch()
      NClk(1)
      Compare("EvenLine ff ",{EvenLine},1,",FLAKEY TEST ",2)
      Switch()
      NClk(1)
      Compare("EvenLine ff ",{EvenLine},0,",FLAKEY TEST ",3)
   ]
   ifnot
   [
      Switch()
      NClk(1)
      Compare("EvenLine ff ",{EvenLine},1,",bad guy ",4)
      Switch()
      NClk(1)
      Compare("EvenLine ff ",{EvenLine},0,",bad guy ",6)
   ]
      
   Stop()
]
//Even or odd,EvenLine ff is just fine,thank you,take it or leave it. OK, OK I was just Czeching
//**************************************************************************************