//**************************************************************************************
//*** UTVFC2.TST
//*** Updated for Rev.H May 25.1979
//*** Updated for Rev.F January 24. 1979
//*** Updated for Rev.D2 November 28,1978
//*** Rev.B June 29.1978
//*** V. Vysin
//**************************************************************************************
//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"
//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL: Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
let Test21() be
[
Start()
//SubTest 21.0 to check the IAR,AAR register (p.6)and TSR(p.4)
Reset() //this'll clear CR &SCR
let i =#40
until i eq 0 do
[
{ODataM} = i ; // bit 0&1 must remain 0 to force both loads
ClkStart()
NClk(1) // loads AAR
ClkIAR() // loads IAR
PrepareTSR()
for k=1 to 10 do
[
EClock() // shifting...this''ll bring IAR.5 to the Idata.00
]
Compare("Idata.16", {Idata.16}, i & #1,"IAR.5 or test shift register on page 4 fails",1,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 1) & #1,"IAR.4 test shift register on pg. 04 bad",2,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 2) & #1,"IAR.3 or test shift register on pg. 04 fails",3,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 3) & #1,"IAR.2 or test shift register on pg. 04 fails",4,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 4) & #1,"IAR.1 or test shift register on pg. 04 fails",5,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 5) & #1,"IAR.0 or test shift register on pg. 04 fails",6,i)
EClock()
Compare("Idata.16", {Idata.16}, 0, "AAR.7 or test shift register on page. 04 failed",7,i)
EClock()
Compare("Idata.16", {Idata.16}, 0, "AAR.6 or test shift register on page. 04 failed",8,i)
EClock()
Compare("Idata.16", {Idata.16}, i & #1,"AAR.5 or test shift register on page. 04 failed",9,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 1) & #1,"AAR.4 or test shift register on page. 04 failed",10,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 2) & #1,"AAR.3 or test shift register on page. 04 failed",11,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 3) & #1,"AAR.2 or test shift register on page. 04 failed",12,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 4) & #1,"AAR.1 or test shift register on page. 04 failed",13,i)
EClock()
Compare("Idata.16", {Idata.16}, (i rshift 5) & #1,"AAR.0 or test shift register on page. 04 failed",14,i)
{IValid'} =1
EClock()
i = i rshift 1
EndTSR()
]
Stop()
]
// IAR and AAR are now registered as good guys. Also,the test shift register is working.
//**************************************************************************************
and Test22() be
[
Start()
//SubTest 22.0 to check Control Phase (p.6)and Blank Terminal (p.7)ffs
Reset() //this'll clear CR and SCR
Switch()
NClk(1) //these two in case ControlPhase starts HI
{ODataM} =#100; // 0 to force AAR load
EClock() // loads ODR
ClkStart() // loads SAR
NClk(1) // loads AAR with 0
{OData3} =#12 ; // set CPhase,PSwitch
WriteHorCont() // writes into HeRAM
NClk(1) // loads v1 reg
NClk(1) // sets ControlPhase & locks it
Compare("ControlPhase ", {ControlPhase}, 1,"did not set!? ",1)
Compare("BlankTerminal ", { BlankTerminal }, 0,"should still be reset ",2)
{OData3} = 2 ; // Switch only,we must drop setCPhase
WriteHorCont() // writes into HeRAM
NClk(1) // Switch =1 now,SetCPhase=0
Compare("BlankTerminal ", { BlankTerminal }, 1,"should have set ",3)
Reset()
{OData3} = 0 ; // clean-up
WriteHorCont() // writes 0000 into HeRAM
NClk(1) // Switch =0 ,resets ControlPhase,loads AAR with xeros, loads SCR
Compare("ControlPhase ", {ControlPhase}, 0,"sb low now ",4)
Compare("BlankTerminal ", { BlankTerminal }, 1,"should still be set ",5)
NClk(1)
Compare("BlankTerminal ", { BlankTerminal }, 0,"sb low again ",6)
Compare("EvenField ", { EvenField }, 1,"shb set! ",7)
//Sub Test 22.1 to check counting in AAR and IAR
//For this test it is vital to have a clear conscience and Hor.Control RAM. Since AAR counts during this test(memory address),we would get interesting results from the test and on the memory output.
for radr=0 to 63 do
[
{ODataM} = #200 + radr ; // force AAR load
ClkStart()
NClk(1)
{OData3} = 0 ; // clean-up
WriteHorCont() // writes 0000 into HcRAM
{ODataM} = #300 ; // to permit counting in AAR
ClkStart()
for inc=1 to 3 do
[
NClk(1) //to write also into addresses notequ 0 mod4
{OData3} = 0 ;
WriteHorCont() // writes 0000 into HcRAM
]
]
let exp2=table[ #1; #2; #4; #10; #20; #40; #100; #200 ]
for k=0 to 7 do
[
ClearNCount()
for v=1 to exp2!k do
[
NClk(1) // increments AAR 1,2,4,8..times.. f(k)
]
// for some reason the Nclk(v) subrut.doesnotwork
PrepareTSR()
for m=1 to 10 do
[
EClock() // shifting...this''ll bring IAR5 to the Idata.00
]
for n=0 to 5 do
[
Compare("Idata.16", {Idata.16},0," IAR somewhere fails",8,k)
EClock() // shifting..
]
for o=0 to 7 do
[
let c=10*k+o
Compare("Idata.16",{Idata.16},(exp2!k)rshift o & #1,"Counting in AAR fails badly",11,c)
EClock() // shifting..
]
EndTSR()
]
for k=0 to 5 do
[
ClearNCount()
for r=1 to exp2!k do
[
ClkIAR() // increments IAR
]
PrepareTSR()
for m=1 to 10 do
[
EClock() // shifting...this''ll bring IAR5 to the Idata.00
]
for o=0 to 5 do
[
Compare("Idata.16",{Idata.16}, (exp2!k)rshift o & #1,"Counting in IAR fails badly ",12,k)
EClock() // shifting..
]
for n=0 to 7 do
[
Compare("Idata.16", {Idata.16},0 ,"AAR fails to remain in xeros ",13,k)
EClock() // shifting..
]
EndTSR()
]
Stop()
]
and ClearNCount() be
[
{ODataM} = 0
ClkStart()
NClk(1)
ClkIAR()
{ODataM} = #300 ; // enables counting by Nclk
ClkStart()
]
//AAR and IAR both count and load well.Well...
//**************************************************************************************