//D0 Card Tester Program for EtherNet
//Test3: Input Buffer Test
//R. Garner August 1, 1978 12:56 AM

//R. Crane November 6, 1978 5:24 PM

get "testdefs.d"
get "spgxwtest.d"

//{IData:IData.00,IData.01,IData.02,IData.03,IData.04,IData.05,IData.06,IData.07,IData.08,IData.09,IData.10,IData.11,IData.12,IData.13,IData.14,IData.15}
//{OData:OData.00,OData.01,OData.02,OData.03,OData.04,OData.05,OData.06,OData.07,OData.08,OData.09,OData.10,OData.11,OData.12,OData.13,OData.14,OData.15}
//{CTask:CTask.0,CTask.1,CTask.2,CTask.3}
//{U63A’:U63A’.0,U63A’.1,U63A’.2,U63A’.3}
//{U63D:U63D.0,U63D.1,U63D.2,U63D.3}
//{U63Q’:U63Q’.0,U63Q’.1,U63Q’.2,U63Q’.3}
//{InSRC:H0,H1,H2,H3}
//{IAddr:IAddr.0,IAddr.1,IAddr.2,IAddr.3,IAddr.4,IAddr.5,IAddr.6,IAddr.7}
//{IConds:InDiffNE0,InDiffNE15,InDiffGE4,InDiffLE11}
//{RData’:RData.0’,RData.1’,RData.2’,RData.3’,RData.4’,RData.5’,RData.6’,RData.7’}
//{TData’:TData.0’,TData.1’,TData.2’,TData.3’,TData.4’,TData.5’,TData.6’,TData.7’}
//{Excess:IData.08,IData.09}
//{RamClock:RamClockFeed’,RamClockFeed’}
//{EClock:EdgeClockFeed’,EdgeClockFeed’}
//{PreRClk:PreRClock,PreRClock}
//{LoadHalfCAddr:SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’}

let Test3(auto,Size,TChar,enable) be
[
if (auto eq false) do
[
let TChar,Size=nil,nil
Wss(D,"*nTest3:EN Input Test; How many words should be received(0-i=18)(18=>overrun)?")
while Endofs(keys) do []
let char=Gets(keys)
switchon char into
[
case$1:Size=1;endcase
case$2:Size=2;endcase
case$3:Size=3;endcase
case$4:Size=4;endcase
case$5:Size=5;endcase
case$6:Size=6;endcase
case$7:Size=7;endcase
case$8:Size=8;endcase
case$9:Size=9;endcase
case$a:Size=10;endcase
case$b:Size=11;endcase
case$c:Size=12;endcase
case$d:Size=13;endcase
case$e:Size=14;endcase
case$f:Size=15;endcase
case$g:Size=16;endcase
case$h:Size=17;endcase
case$i:Size=18;endcase
default:return
]
Wss(D,"*nDo you want to set bad status(y)(Size=1,2,4,7,8,b,d,e,g)?")
while Endofs(keys) do []
let TChar=Gets(keys)
]
let SP,S,Savei=nil,nil,nil
{Run}=0
{SRClock}=0
{LoadHalfCAddr}=ICA;//InCAddr=12
{LoadHalfCAddr}=OCA;//OutCAddr=5
{CTask}=12
{IValid’}=1
{MC2StartXport}=0
{OValid’}=1
{AdvPipe’}=1
{OFault’}=1
{Phase1Next’}=1; //so no transmit
{EdgeClockFeed’}=1
{RamClockFeed’}=1
Wss(D,"*nTest3a: Write IB")
Position(enable,"B(16)","U63","B(16)","i14");//Low 4-bit Ram
Position(enable,"C(16)","U24","C(16)","h10");//IConds
Position(enable,"D(16)","U1","D(16)","g10");//InSRC
Position(enable,"E=PlatformClip","Z54Z","E=PlatformClip","e5")
{SRData}=0;{SRData’}=1
{Carrier}=0
{TClock}=1;{TClock’}=0
{PreamDet’}=1
{PreRClock}=0
{Collision}=0
for i = 1 to 17 do {PreRClk}=PreRclick; //enough to clear PacketInMode
{EClock}=Eclick;//enough to clear out a possible Wire Write
{EClock}=Eclick
{EClock}=Eclick
{Run}=1
//Enable Input
LoadState(300B,220B)
//Set PacketInMode
{PreamDet’}=0;
{PreamDet’}=1;
{Carrier}=1;
Compare({PacketInMode},0,"PacketInMode")
{SRData}=0;{SRData’}=1
{PreRClk}=PreRclick;//first data bit
Compare({PacketInMode},1,"PacketInMode")
//load the Input Buffer via Input Shift Register
for i = 1 to Size do
[
for j = 0 to 1 do
[
for k = 1 to 7 do
[
{SRData}= i rshift (7-k);{SRData’}= not(i) rshift (7-k)
{PreRClk}=PreRclick
]
Compare({InSRC},((j+1)*8) - 1 & 17B,"InSRC");//InSRC should be 7 or 15
{SRData}=0;{SRData’}=1;//1st bit of byte
if i eq Size & j eq 0 & TChar eq $y then//for Bad Alignment
[
{Carrier}=0
{SRData’}=0
{PreRClk}=PreRclick;//Load PreIB,PreESP,Reset PktOutMode
//next preRClock zeroes InSRC
]
if i eq Size & j eq 1 then//normal case
[
{Carrier}=0
{SRData’}=1
]
{PreRClk}=PreRclick;//Load PreIB,1st Bit of Byte,Reset PktOutMode
Compare({U63D},not(i) & 17B,"U63 (i14) D")
//Cause WireWrite (Note:This causes the low byte to be written in location
// n and location n+1 !! It also causes Overrun to be incorrectly set
// when Size = 17)
{EClock}=Eclick
{EClock}=Eclick
{RamClockFeed’}=0;//Write IB
{EClock}=Eclick;//Incr WIP, clear WireWrite
{RamClockFeed’}=1
{EClock}=Eclick;//for initial move one word
test j eq 0
ifso
[
unless i eq Size & TChar eq $y do
[
Compare({U63Q’},i & 17B,"U63 (i14) Q’")
Compare({U63A’},not(i-1) & 17B,"U63 (i14) A’")
]
]
ifnot
Compare({InDiffGE4},(((i-1) & 17B) ge 4) & 1,"InDiffGE4")
if i eq Size & j eq 0 & TChar eq $y then goto BadIStat
]
]
BadIStat:Compare({PacketInMode},0,"PacketInMode")
Compare({InSRC},0,"InSRC")
//Read ’em into the D0
Wss(D,"*nTest3b: Read IB")
{IAddr}=303B;//IAddr[0..3]=12; IAddr[4..7]=3
{IValid’}=0
{EClock}=Eclick;//Set ReadData
Compare({U63A’},not(1) & 17B,"U63 (i14) A’")
Compare({U63Q’},2,"U63 (i14) Q’");//second data word
Compare({IData},401B,"IData");//First Data word
Compare({IData.16},1,"IData.16");//First Data word parity
if Size eq 18 % Size eq 17 then goto OverF;// 17 nomally doesn’t cause Overflow
Savei=1
for i = 2 to Size do
[
{EClock}=Eclick;//Load PostIB & Incr DIP
Compare({U63A’},not(i) & 17B,"U63 (i14) A’")
if i ne Size then Compare({U63Q’},(i+1) & 17B,"U63 (i14) Q’");//next data word
S={IData}
SP=not(S<<w.b12 xor S<<w.b13 xor S<<w.b14 xor S<<w.b15 xor S<<w.b4 xor S<<w.b5 xor S<<w.b6 xor S<<w.b7 xor {IData.16}) & 1
test TChar eq $y & i eq Size
ifso
[
Compare(S & 377B,i,"IData");//high byte was written in low byte
Compare(SP,1,"InputParity");//incorrect parity was computed
]
ifnot Compare(SP,0,"InputParity")
Savei=i
]
Compare({InDiffNE0},0,"InDiffNE0")
//Read 2 extra words-overrun’d packet has been aborted
OverF:{EClock}=Eclick;//right number for size of read,bring up IAttnReq
{EClock}=Eclick;//first extra read
{IValid’}=1
{EClock}=Eclick;//second extra read,turn off ReadData
//DIP shouldn’t have changed across reads-DIP=2 for overrun after reads...
unless (Size eq 18 % Size eq 17) do Compare({U63A’},not(Savei) & 17B,"U63 (i14) A’");
//Read Input Status
{IAddr}=122B;//IAddr[0..3]=5; IAddr[4..7]=2
{IValid’}=0
{EClock}=Eclick
S={IData}
test TChar eq $y ifso Compare(S & 100000B,100000B,"Jam Status")
ifnot Compare(S & 100000B,0,"Jam Status")
test Size eq 18 ifso Compare(S & 20000B,20000B,"OverRun Status")
ifnot Compare(S & 20000B,0,"OverRun Status")
test TChar eq $y ifso Compare(S & 400B,400B,"Bad Alignment Status")
ifnot Compare(S & 400B,0,"Bad Alignment Status")
if Size le 16 then Compare({Excess},2,"ExcessCount")
{IValid’}=1
//Set Purge Mode
LoadState(300B,260B)
{EClock}=Eclick;//Set DoneWithInPacket
//Check for zero status
{IAddr}=122B;//IAddr[0..3]=5; IAddr[4..7]=2
{IValid’}=0
{EClock}=Eclick
S={IData} & 124400B
Compare(S,0,"Input Status")
//quiesce
{IValid’}=1
{EClock}=Eclick
Wss(D,"*nEnd of Test3")
]