//D0 Card Tester Program for EtherNet
//Test1: Initital & D0 Interface Check
//R. Garner August 1, 1978 12:53 AM
//R. Crane November 6, 1978 3:19 PM

get "testdefs.d"
get "spgxwtest.d"

//{IData:IData.00,IData.01,IData.02,IData.03,IData.04,IData.05,IData.06,IData.07,IData.08,IData.09,IData.10,IData.11,IData.12,IData.13,IData.14,IData.15}
//{OData:OData.00,OData.01,OData.02,OData.03,OData.04,OData.05,OData.06,OData.07,OData.08,OData.09,OData.10,OData.11,OData.12,OData.13,OData.14,OData.15}
//{CTask:CTask.0,CTask.1,CTask.2,CTask.3}
//{U57A’:U57A’.0,U57A’.1,U57A’.2,U57A’.3}
//{U57D:U57D.0,U57D.1,U57D.2,U57D.3}
//{U57Q’:U57Q’.0,U57Q’.1,U57Q’.2,U57Q’.3}
//{IAddr:IAddr.0,IAddr.1,IAddr.2,IAddr.3,IAddr.4,IAddr.5,IAddr.6,IAddr.7}
//{IConds:InDiffNE0,InDiffNE15,InDiffGE4,InDiffLE11}
//{RData’:RData.0’,RData.1’,RData.2’,RData.3’,RData.4’,RData.5’,RData.6’,RData.7’}
//{TData’:TData.0’,TData.1’,TData.2’,TData.3’,TData.4’,TData.5’,TData.6’,TData.7’}
//{RamClock:RamClockFeed’,RamClockFeed’}
//{EClock:EdgeClockFeed’,EdgeClockFeed’}
//{PreRClk:PreRClock,PreRClock}
//{TClk:TClock,TClock’,TClock,TClock’}
//{LoadHalfCAddr:SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’,SRClock,SRClock,SRDataIn’}

let Test1(enable) be
[
Wss(D,"*nTest1:Init&D0Interface")
Wss(D,"*nRemove Platform Z54Z (e5)")
Position(enable,"E=PlatformClip A","Z54Z","E=PlatformClip A","e5")
Position(enable,"E=PlatformClip B","U84","E=PlatformClip B","b15")
Position(enable,"E=PlatformClip C","U80","E=PlatformClip C","f13")
{Run}=0
{CTask}=0
{IAddr}=0
{OData}=0
{OData.16}=0
{SRDataIn’}=1
{SRClock}=0
{IValid’}=1
{OValid’}=1
{AdvPipe’}=1
{MC2StartXport}=0
{OFault’}=1
{Phase1Next’}=1; //so no transmit
{EdgeClockFeed’}=1
{RamClockFeed’}=1
{SRData}=0
{SRData’}=1
{Carrier}=0
{TClock}=1
{TClock’}=0
{PreRClock}=0
{Collision}=0
{PreRClk}=PreRclick
{TClk}=Tclick; //enough to clear OutSRC
{TClk}=Tclick
{EClock}=Eclick;//enough to clear out a possible Wire Read
{Phase1Next’}=0; //so no transmit, must go to 0 to initialize
{EClock}=Eclick
{Phase1Next’}=1; //so no transmit
{EClock}=Eclick
WaitForKey("*nBoard reset, Check voltages +5,+12,-5,SKY,& GND")
Wss(D,"*nTest1a: Xerox Wire Static Reset Test")
//Check some reset values
Compare({Transmit},0,"Transmit")
Position(enable,"C(20)","U28","C(20)","e12")
Compare({DoneWithInPacket’},0,"DoneWithInPacket’")
Compare({OutAttnReq},0,"OutAttnReq")
Compare({InWakeReq’},1,"InWakeReq’")
Compare({OutWakeReq’},1,"OutWakeReq’")
Wss(D,"*nTest1b:Dynamic Tests")
{Run}=1
//Load CAddr chips U90 (b19) shift register or U115 (c19) output buffer in this path
InitCAddr(2B,14B,5B,0,0)
//Check CTask
if PWA do
[
Position(enable,"B(14)","U75","B(14)","U75")
Position(enable,"D(14)","U97","D(14)","U97")
Compare({CTask=ITask’},1,"CTask=ITask’")
{CTask}=14B
Compare({CTask=ITask’},0,"CTask=ITask’")
Compare({CTask=OTask’},1,"CTask=OTask’")
{CTask}=5
Compare({CTask=OTask’},0,"CTask=OTask’")
Compare({CTask=ITask’},1,"CTask=ITask’")
]
if not PWA do
[
Position(enable,"D(14)","c16","D(14)","c16") ;//CTas is CTask for Stitchweld board
Compare({CTas=ITas’},1,"CTask=ITask’")
{CTask}=14B
Compare({CTas=ITas’},0,"CTask=ITask’")
Compare({CTas=OTas’},1,"CTask=OTask’")
{CTask}=5
Compare({CTas=OTas’},0,"CTask=OTask’")
Compare({CTas=ITas’},1,"CTask=ITask’")
]
//Check IMeF
{IAddr}=300B;//IAddr[0..3]=12; IAddr[4..7]=0
{IValid’}=0
{EClock}=Eclick
Compare({IMeF’/a},0,"IMeF’/a")
Compare({IData},2402B,"XWDevID");//Check for read of device ID
{IAddr}=120B;//IAddr[0..3]=5; IAddr[4..7]=0
{EClock}=Eclick
Compare({IMeF’/a},0,"IMeF’/a")
Compare({IData},2401B,"XWDevID");//Check for read of device ID
{IValid’}=1
{EClock}=Eclick
Compare({IMeF’/a},1,"IMeF’/a")
//Check OMeF
Compare({OMeF},0,"OMeF")
{IAddr}=120B;//IAddr[0..3]=5; IAddr[4..7]=0
{AdvPipe’}=0
{EClock}=Eclick
{MC2StartXport}=1
{EClock}=Eclick
{OValid’}=0
{EClock}=Eclick
Compare({OMeF},1,"OMeF")
{IAddr}=300B;//IAddr[0..3]=12; IAddr[4..7]=0
{EClock}=Eclick
{EClock}=Eclick
{EClock}=Eclick
Compare({OMeF},1,"OMeF")
{OValid’}=1
{MC2StartXport}=0
{EClock}=Eclick
Compare({OMeF},0,"OMeF")
// State Reg should be zero
{IAddr}=122B;//IAddr[0..3]=5; IAddr[4..7]=2
{IValid’}=0
{EClock}=Eclick
Compare({IData} & 77B,0,"State")
// all ones test of state reg
LoadState(120B,337B)
{IAddr}=302B;//IAddr[0..3]=12; IAddr[4..7]=2
{EClock}=Eclick
Compare({IData} & 77B,37B,"State")
LoadState(120B,377B)
{IAddr}=302B;//IAddr[0..3]=12; IAddr[4..7]=2
{EClock}=Eclick
Compare({IData} & 77B,77B,"State")
// all zeros test of state reg
LoadState(120B,300B)
{IAddr}=122B;//IAddr[0..3]=5; IAddr[4..7]=2
{EClock}=Eclick
Compare({IData} & 77B,0,"State")
{IValid’}=1
{EClock}=Eclick
Wss(D,"*nEnd of Test 1")
]