//D0 Card Tester Program for EtherNet
//R. Garner July 27, 1978 11:08 PM
//R. Crane November 23, 1978 3:05 AM
get "testdefs.d"
get "spgxwtest.d"

//{IAddr:IAddr.0,IAddr.1,IAddr.2,IAddr.3,IAddr.4,IAddr.5,IAddr.6,IAddr.7}
//{OData:OData.00,OData.01,OData.02,OData.03,OData.04,OData.05,OData.06,OData.07,OData.08,OData.09,OData.10,OData.11,OData.12,OData.13,OData.14,OData.15}
//{EClock:EdgeClockFeed’,EdgeClockFeed’}
//{SRClick:SRClock,SRClock}
//{PreRClk:PreRClock,PreRClock}
//{TClk:TClock,TClock’,TClock,TClock’}
//{QuickClk:TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock,TClock}
//{LoadOAddr:MC2StartXport,EdgeClockFeed’,EdgeClockFeed’,MC2StartXport,EdgeClockFeed’,EdgeClockFeed’,AdvPipe’,EdgeClockFeed’,EdgeClockFeed’,AdvPipe’}
;// **The LoadODat below requires one EClock following it to get data to register.**
//{LoadODat:OValid’,EdgeClockFeed’,EdgeClockFeed’,OValid’}

static [ D=0; PWA=0]

let main() be
[
let DispBlock = vec 10000
D=CreateDisplayStream(30,DispBlock,10000)
if (D eq 0) do [ Ws("Couldn’t open Display Stream");finish ]
ShowDisplayStream(D)
[
Wss(D,"*nThis is the D0 Ethernet Card Test Program. It can test either the")
Wss(D,"*nprinted circuit board (PWA) or the stitchweld version (SW). Which ")
Wss(D,"*ncard do you wish to test? P-PWA S-SW .....")
while Endofs(keys) do []
let char=Gets(keys)
if ((char eq $S) % (char eq $s)) do
[
PWA=false
Wss(D," -STITCHWELD-")
]
if ((char ne $S) & (char ne $s)) do
[
PWA=true
Wss(D," -PRINTED WIRING ASSEMBLY-")
]
Wss(D,"*n")
Wss(D,"*nWhich Test(1-Interface,2-Output,3-Input,4- TimerTest, A-Automatic)?")
Wss(D,"*n (Automatic does all except TimerTest.)*n")
while Endofs(keys) do []
let char=Gets(keys)
switchon char into
[
case $1:Test1(true)
endcase
case $2:Test2A(false,2,"n",true)
endcase
case $3:Test3(false,2,"n",true)
endcase
case $4:TimerTest()
endcase
default:AutoTest()
]
] repeat
]

and AutoTest() be
[
Test1(true);//Parameter true enables clip positioning
Test2A(true,2,"n",true);// (auto test enable,# words, set bad status, enable clip position)
Test2A(true,8,"n",false)
Test2A(true,11,"n",false)
Test2A(true,12,"n",false)
Test2A(true,11,"y",false)
Test3(true,2,"n",true)
Test3(true,10,"n",false)
Test3(true,17,"n",false)
Test3(true,18,"n",false)
Test3(true,11,"y",false)
]

and Position(enable,clip,pos,clipb,posb) be
[
if (enable & PWA) do
[ WaitForKey(FORMATN("*nPlease place clip <S> at location <S>",clip,pos))]
if (enable & not PWA) do
[ WaitForKey(FORMATN("*nPlease place clip <S> at location <S>",clipb,posb)) ]

return
]

and WaitForKey(msg) be
[
Wss(D,msg)
Wss(D," Waiting...")
while Endofs(keys) do [ ]
Gets(keys)
Wss(D," Running...")
]

and Compare(value,correctValue,name) be
[
until value eq correctValue do
[
Wss(D,FORMATN("*nError:<S> is <OCT>, should be <OCT>",
name,value,correctValue))
Wss(D," Waiting...")
while Endofs(keys) do [ ]
let char = Gets(keys)
//if (char eq $R % char eq $r) loop
Wss(D," Running...")
break
]
return
]

and LoadState(IAddr,value) be
[
{IAddr}=IAddr
{LoadOAddr}=134B ;// Load IAddr into Output Address Reg.
{OData}=value;
{LoadODat}=14B;//Load the Out Data Reg.
{EClock}=Eclick;//reset OMeF, write StateReg
return
]

;// This part initializes and tests Controller Address (CAddr) register ;

and InitCAddr(NumTask,CAddrA,CAddrB,CAddrC,CAddrD) be
[
let CAddr = CAddrA % CAddrB lshift (4) % CAddrC lshift (8) % CAddrD lshift (12);
let SRWord = not CAddr;
for i = 1 to (4*(NumTask)) do
[
{SRDataIn’} = SRWord
{SRClick} = 2
SRWord = SRWord rshift 1
]
SRWord = not CAddr;
for i = 1 to (4*(NumTask)) do
[
{SRDataIn’} = SRWord
{SRClick} = 2
SRWord = (SRWord rshift 1) %( {SRDataOut’} lshift 15)
]
SRWord = (not SRWord) rshift (15 - (4*(NumTask)))
Compare(SRWord,CAddr," Check chips U90 (b19) or U115 (c19) on page 1 if error. CAddr")
]
and TimerTest () be
[
Wss(D,"*nThe timer test triggers the one shots in the receive circuit to allow")
Wss(D,"*nchecking. It assumes proper operation of the rest of the controller to")
Wss(D,"*ntrigger the one shots. If ALL the one-shots are firing, then it can be assumed")
Wss(D,"*nthat the rest of the controller is working for the purpose of this test.")
Wss(D,"*nOtherwise, run other tests to locate problem.")
Wss(D,"*nWith a calibrated oscilloscope, check the following 4 pins for pulses of")
Wss(D,"*nspecified width below. Measure width at 1.3 V point of waveform. Signals can")
Wss(D,"*nbe found on pages 14 &15 of schematics. Be sure special test clip assembly")
Wss(D,"*nis plugged into socket E of tester and position Z54Z (e5) of board.*n")
Wss(D,"*nSignal Name PWA (SW) Location Width Type*n")
Wss(D,"*n XOP U12.10 (f6.10) >55nS & <65nS Positive pulse")
Wss(D,"*n IH U12.5 (f6.5) >245nS & <275nS Positive pulse")
Wss(D,"*n Carrier U21.5 (f6.13) >460 nS & <500nS Positive pulse")
Wss(D,"*n LastRClock U21.4 (e7.12) >55ns & <100nS negative pulse")

;//************** Set Up IAddr Lines *************************************************************
InitCAddr(2B,14B,5B,0,0);//Initialize Controller Addr. Reg. IAddr=14 OAddr=14B
LoadState(120B,320B);//Enable input half of board
{IAddr}=120B;// State Register is selected
{LoadOAddr}=134B ;// Load IAddr into Output Address Reg.
{OData}=334B;//Loopback=1, ResetInput’=1, EOP=1, Others = 0
{LoadODat}=14B;//Load the output Reg.
;//************** Enable LastRClock one-shot ******************************************
{Carrier}=1;//This and following receive clock make
;// PacketInMode=1
{PreRClk}=PreRclick;// PacketInMode=1 enabling LastRClock one-shot
;//************** Loop ******************************************************************
{OValid’}=0;// Get ready for output loop
while Endofs(keys) do
[
;//******** Trigger XOP pulse and IH, Carrier, and LastRClock one-shots *******
;//************** This loop takes 150 uS *************************************
{OData.12}=1;//Loopback = 1 causing transition on SRDataEM
{EClock}=Eclick;//Load the Data
{OData.12}=0;//Loopback = 0 causing transition on SRDataEM
{EClock}=Eclick;//Load the Data
]
{OValid’}=1;// Clean up after output loop
;//************** Set Signals ************************************************************
{Carrier}=0;// So PktOutMode can be enabled in loop
{SRData’}=1;// So PktOutMode can be enabled in loop
{Collision}=1;//Set collision to enable Jam pulse
Wss(D,"*n*nNow look at Jam line.*n")
Wss(D,"*n Jam U12.13 (e7.13) >2.7uS & <3.3uS positive pulse");
Gets(keys)
;//************** Loop ******************************************************************
while Endofs(keys) do
[
;//************** Trigger Jam One-Shot ******** This loop takes 4 mS ********
{IAddr.7}=0 ;//Clear bit 7 to specify status reg...Other bits same.
{LoadOAddr}=134B; // Load Status Reg. Addr. into Output Address Reg.
{OData.14}=0 ;//ResetOutput’=0 disabling output & clearing Jam
{LoadODat}=14B;//Load the Data
{OData.14}=1 ;//ResetOutput’=1 enabling output & Jam
{LoadODat}=14B;//Load the Data
{IAddr.7}=1;//Set bit 7 to specify data reg...Other bits same.
{LoadOAddr}=134B ;// Load OutBuffer Addr. into Output Address Reg.
{LoadODat}=14B ;//Output a garbage word to increment DOP
{EClock}=Eclick;//Extra clocks to get Wr. Data pulse & incr. DOP
{EClock}=Eclick;//Conditons are now set up to allow SendMode=1
{QuickClk}=52525B;//21 T clocks are necessary to get SendMode=1
{QuickClk}=52525B;// 3x8 = 24 T clocks sent
{QuickClk}=52525B;

]

Gets(keys)
LoadState(120B,300B);//Reset Everything i.e. Status Reg.=0
Wss(D,"*nTimer test done.")
]