[Cyan]<D0>IOcardtests.disk!1>spgentest.memo

3. 3 cable assemblies with 16 pin DIP plug on one end and 16 pin clip on other end and 20 inch lead.
Plug wires 1-16 go to clip leads 1-16.

4. 1 cable assembly with 16 pin DIP plug and 20 pin clip with 20 inch lead and wired as shown
Plug pins 1-8 to clip 1-8
Plug pins 9-16 to clip 12-19

5. 1 cable assembly with 16 pin DIP plug on one side with two 16-pin clips and one 16 pin platform on the other side. Wire length between plug and clip or plaftorm is 14 inches. Connections are:

Plug pins 9-16 to Platform A pins 9-16 (Z54Z or e5 on SW)
Plug pin 1 to clip B pin 2 (U84 or b15 on SW)
Plug pin 2 to clip B pin 14 (U84 or b15 on SW)
Plug pin 3 to clip B pin 11 (U84 or b15 on SW)
Plug pin 4 to clip C pin 12 (U80 or f13 on SW)
Plug pin 5 to clip C pin 9 (U80 or f13 on SW)

1. Visually check board for loose chips, card extractors and stiffeners present, connector on back side of board for PWA’s, and locking posts for connector. There should be 2 flat washers between the front connector surface and the locking post, with the lockwasher and nut on the back side. The connector should be fastened to the board with two screws and nuts.

2. Insert card into card tester and power on. Check that +5 volt current drain is about 7 amperes. The +12 volt current drain is .030 A with no transceiver and .09 A with transciever. The -5 volt current drain is 0. The +15 volt output from switching power supply (I/O connector pin 19) should be within .5 volt of 15 volts. If current drain is 0, check fuses near edge connector on board. If too high, look for shorts or bad components. The only load on +12 volt supply is the switching supply whose diagrams and waveforms are on page 16 of logic drawings.

1. Insert card into tester, remove platform Z54Z and lift pins 1 & 2 of 74S51 chip U54 (b11). On early PWA boards, U54 has a jumper, so just leave chip dangling and insert (for duration of test) another S51 without jumper.

This program is divided into 3 sections; D0 Interface tests, Output tests and Input tests. It starts by asking which test is desired. A specific section can be indicated, or automatic which runs the interface test, the output test with 5 sets parameters, and the input test with 5 sets of parameters. A fourth test, Timer Test, permits checking the one-shot timing. The user is instructed to place clip leads and platforms on the board as necessary.

When plugging clip leads into the tester, pin 1 of the clip lead is marked with an arrow, dot, or notched corner. The clips should have a dot near pin 1. The program makes requests in the form "Place clip B(14) at location U75". The B means use socket B on the tester. (14) is the number of pins on the chip. For 14 pin chips and 16 pin clips, orient pin 1 of clip on pin 1 of chip. 16 pin clips are used for 14 and 16 pin chips. 20 pin clips are used for 20 pin chips. U75 is a board location. If an entry such as (b11) follows, it is the stitchweld board location.

An error will cause the program to temporarily stop and indicate the signal name along with the bad and correct values. The signal names can be found in the schematic diagrams. If a signal is flagged as incorrect, refer to the logic diagram and trace it back to a point of inconsistency. At some point, reference to the card test program listing may be necessary to see what signal is being set. Some information is given below, but the two primary sources of information are the logic diagrams and the card tester program listing. The only other sources of information are the timing diagrams and people.

Following an error, any input from the keyboard will cause the program to continue. There is currently no way to retest a signal after an error is reported without going back to the beginning of the particular section.

Pressing left shift and SWAT keys together will cause the program to abort and return to the Alto executive. Turn card tester power on before starting the card test program and do not turn it off until the program is done. Turning it off in the middle of the program will cause the tester and board to lose their state making it necessary to restart the program.

Test 1 checks the D0 interface in the controller. This includes pages 1,2, 13, and part of page 12 of the logic drawings. Clips will go onto chips U84 (b15), U28 (e12), U75, U97, and (c16).

This is diagramed on pages 8-12, and part of page 14 of logic diagrams. If this test is started separately, it will ask for two parameters; packet size and whether or not it should test for bad status. The bad status test will only work with packets smaller than 12 words. Program does not work with packet size of 1. The parameters used in the automatic test are:
Packet SizeCheck Status
2N (=No)
8N
b (=11)N
c (=12)N
b (=11)Y
Clips will go onto chips U57 (f16), U47 (f14), U7 (c10), U80 (f13) and U84 (b15).

This is diagramed on pages 3-8, and part of page 15 of logic diagrams. If this test is started separately, it too will ask for same parameters. In this case, bad status test requires packet sizes of 1,2,4,7,8,11,13,14, or 16. The parameters used in the automatic test are:
Packet SizeCheck Status
2N (=No)
a (=10)N
h (=17)N
i (=18)N
b (=11)Y
Clips will go onto chips U63 (i14), U24 (h10), and U1 (g10).

A fourth section, called timer test, permits testing the one-shots used in the receiver. To do this run test 4, the Timer test part of the test program.
Check U12.10 for 60 nS + 5 nS positive pulses.
Check U12.5 has 260 nS + 15 nS positive pulse.
Check U21.5 has 480 nS + 20 nS positive pulse.
Check U21.4 has 80 nS + 20 nS negative pulse.

When these are checked, hit the space bar and check U12.13 for 3 + .3 microsecond positive pulse.

3. The card test program coverage is between 70% and 80%. For coverage of remaining parts, and checking for dynamic faults, use the D0 test program, Packets.