[Cyan]<D0>IOcardtests.disk!1>rdcmacros.tst

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{IAddr: Iaddr.0, Iaddr.1, Iaddr.2, Iaddr.3, Iaddr.4, Iaddr.5, Iaddr.6, Iaddr.7}
//{IData: Idata.00, Idata.01, Idata.02, Idata.03, Idata.04, Idata.05, Idata.06, Idata.07, Idata.08, Idata.09, Idata.10, Idata.11, Idata.12, Idata.13, Idata.14, Idata.15}
//{OData: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07, Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{WakeP’: WakeP3’, WakeP2’, WakeP1’}
//{FormatCon1: dForCnt.1, dForCnt.2, dForCnt.3, dForCnt.4, dBrOnSync, dSequenceEnd, dSectorWake’, dClrDevOp’, dXferTime, dSyncTime, dDataTime, dCRCShift, dCRCWrite, dCRCCheck, dWriteGate, dReadGate}
//{FormatCon2: dECCClear, dECCShift, dECCWrite, dECCCheck}
//{BufferCon: dBrCnt.2, dIncCntr, dClrCntr’, dLdCntr’, dBrCry, dBrXfer, dDataWake, dClrMemBufAdr’, dIncDevBufAdr, dDev←Buf, dWriteBuf, dRateErrorPossible}
//{ForSeqAdr: ForSeqAdr.0, ForSeqAdr.1, ForSeqAdr.2, ForSeqAdr.3, ForSeqAdr.4, ForSeqAdr.5, ForSeqAdr.6, ForSeqAdr.7}
//{BufSeqAdr: BufSeqAdr.0, BufSeqAdr.1, BufSeqAdr.2, BufSeqAdr.3, BufSeqAdr.4, BufSeqAdr.5, BufSeqAdr.6, BufSeqAdr.7}

//**************************************************************************************
//To define the global variabes
static
[
ParErr = 0
idt = nil
again = false
]

//**************************************************************************************
//IData Macro:
//IData(Addr):
//arg1: Input Register Address mnemonic
//idt is given value of Odata[00:15]

let IData(Addr) be
[
SetCaddr()
{IAddr} = (Caddr lshift 4 ) % Addr
{IValid’} = 0
Clocks()
idt = {IData}
let ParBit = {Idata.16}
Breakpoint(8, {IAddr}, idt, ParBit)
{IValid’} = 1
Clocks()
ParErr = 0
let parity = 0//Parity check of Idata
let x = idt
for i = 0 to 15 do
[
parity = parity + (x & 1b)//"+" is faster than "XOR"
x = x rshift 1
]
if (parity & 1) eq ParBit then ParErr = 1
]

//OData Macro:
//OData(Addr, Data, n, Mod)
//Addr: Output Register Address mnemonic
//Data: Initial Data = Odata[00:15]
//n: Number of data words to output; Default=1.
//Mod: Data modifier when n > 1; Default=0.

and OData(Addr, Data, n, Mod; numargs na) be
[
DefaultArgs(lv na, -1, 0, 1, 0)
SetCaddr()
{IAddr}=(Caddr lshift 4 ) % Addr
{AdvancePipe’} = 0
Clocks()

{AdvancePipe’} = 1
{MC2StartXport} = 1
Clocks()

{MC2StartXport} = 0
{OValid’} = 0
L1: {OData} = Data
Clocks()
let parity = 0//Parity generation for Odata
let DataP = Data
for i = 0 to 15 do
[
parity = parity + DataP//"+" is faster than "XOR"
DataP = DataP rshift 1
]
{Odata.16} = not (parity & 1)
Breakpoint(7, {IAddr}, {OData}, {Odata.16})

n = n - 1
test n eq 0
ifso
[
{OValid’} = 1
Clocks()
]

ifnot
[
Data = Data + Mod
goto L1
]
]

//Comparison routine
and Compare(item, is, sb, msg, sp, IDno, index; numargs na) = valof
[
DefaultArgs(lv na, -3, "No data.", 0, 0, 0)
if is eq sb then resultis true
failures = failures + 1
test looping
ifso
[
unless Endofs(keys) do
[
Gets(keys)
finish
]
resultis false
]
ifnot
[
DisplayString(FORMATN("*nFAILURE: SubTest <D>.<D>.<D>; <S> is <B>b; Should be = <B>b. <S>", testno, IDno, index, item, is, sb, msg))
SpaceDisplay(sp)
DisplayString("*nDepress q to quit; l to loop from start of test to failure; any other key to continue.")
Delay(1)
if cont eq false do [] repeatwhile Endofs(keys)
unless Endofs(keys) do
[
let ch = Gets(keys)
switchon (ch & #177) into
[
case $l:
case $L: looping = not looping; endcase;
case $q:
case $Q: finish
]
]
if looping eq true do
[
DisplayString(FORMATN("*nTEST <D> LOOPING; depress any key to quit.", testno))
SpaceDisplay(4)
resultis false
]
resultis true
]
]

//Clocking routines
and RClock() be //RamClkFeed’ is normally high
[
{RamClockFeed’} = 0
{RamClockFeed’} = 1
]

and EClock() be //EdgeClkFeed’ is normally high
[
{EdgeClockFeed’} = 0
{EdgeClockFeed’} = 1
]

and Clocks() be
[
RClock()
EClock()
]

and SRClock() be //SRClock is normally high
[
{SRClock} = 0
{SRClock} = 1
]

and EnableDevClk() be
[
for n = 0 to 15 do
[
OData(TestRegLd, 401b)
OData(TestRegLd, 400b)
]
]

and Start() be
[
//Set up the title display
if looping eq false do [ DisplayString(FORMATN("*nTEST <D> RUNNING", testno)) ]

//Set up initial conditions
{IData} = ###
{FormatCon1} = 400b
{FormatCon2} = 0
{BufferCon} = 1420b
{ForSeqAdr} = ###
{BufSeqAdr} = ###
{WakeP’} = ###
{RamClockFeed’} = 1
{EdgeClockFeed’} = 1
{Phase1Next’} = 1
{MC2StartXport} = 0
{AdvancePipe’} = 1
{SRClock} = 1
{IValid’} = 1
{OValid’} = 1
{OFault’} = 1
{RUN} = 0
Clocks()
Clocks()
{RUN} = 1
EClock()
OData(TestRegLd, 605b)//Sets Ready, SectorMark, & DevClkSource
OData(TestRegLd, 604b)//Cycles DevClkSource; sets SectorMarkSD
OData(TestRegLd, 204b)//Resets TestMode; First EdgeClk sets SectorMarkSP
for n = 0 to 20 do [ EClock() ]//Sets DevSelOK
]

and Stop() = valof//Stop and total the run time for each test
[
if again do
[
DisplayString(FORMATN("*nEND OF TEST <D> REPEAT.*nDepress d to discontinue repeat; q to quit.", testno))
SpaceDisplay(3)
Delay(1)
unless Endofs(keys) do
[
let ch = Gets(keys)
switchon (ch & #177) into
[
case $d:
case $D: again = false; endcase
case $q:
case $Q: finish
]
]
SpaceDisplay(2)
if again resultis true
]
DisplayString(FORMATN("*nTEST <D> COMPLETE.", testno))
if looping do
[
DisplayString("*nLOOPING True;*nDepress d to discontinue looping on next test; any other key to retain.")
SpaceDisplay(2)
while Endofs(keys) do [ ]
let ch = Gets(keys)
switchon (ch & #177) into
[
case $d:
case $D: looping = false; endcase
]
]
Breakpoint(1)
resultis false
]