[Cyan]<D0>IOcardtests.disk!1>rdc7.tst

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{BufferCon: dBrCnt.2, dIncCntr, dClrCntr’, dLdCntr’, dBrCry, dBrXfer, dDataWake, dClrMemBufAdr’, dIncDevBufAdr, dDev←Buf, dWriteBuf, dRateErrorPossible}
//{BufSeqAdr: BufSeqAdr.0, BufSeqAdr.1, BufSeqAdr.2, BufSeqAdr.3, BufSeqAdr.4, BufSeqAdr.5, BufSeqAdr.6, BufSeqAdr.7}

//**************************************************************************************
//Test71To test:Address Selection

let Test71() be
[
L71: Start()
let adrval = table[ 41b; 141b; 341b; 1b ]
EnableDevClk()
OData(DevOpRegLd, 241b)
OData(ErrReset)//Clears Abort
{dSequenceEnd} = 1
for k = 0 to 2 do//Clear NonComp
[
OData(TestRegLd, 405b)//Sets SectorMark; Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]

//SubTest71.1.n; checks loading of BufSeqAdr
{dSequenceEnd} = 0
for k = 0 to 3 do//Load SeqCnt
[
OData(TestRegLd, 405b)//Sets SectorMark; Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; Load SeqCnt
if not Compare("BufSeqAdr", {BufSeqAdr}, adrval!0, "BufSeqAdr wrong;*n check BufSeqAdr register.", 2, 1) goto L71
{dSequenceEnd} = 1
OData(TestRegLd, 401b)//Cycles DevClk & ByteClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; resets ByteClkEnbl

for n = 1 to 3 do//Produces ByteClk; Inc SeqCnt; transfers SeqAdr to BufSeqAdr
[
for k = 0 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClkSource - 1
OData(TestRegLd, 400b)//Cycles DevClkSource - 0
]
if not Compare("BufSeqAdr", {BufSeqAdr}, adrval!n, "BufSeqAdr wrong;*n check BufSeqAdr register.", 2, 1, n) goto L71
]

{dSequenceEnd} = 0
for k = 0 to 7 do//Produces ByteClk; Inc SeqCnt
[
OData(TestRegLd, 401b)//Cycles DevClkSource - 1
OData(TestRegLd, 400b)//Cycles DevClkSource - 0
]
EClock()//Sets SequenceEndS
EClock()
if not Compare("BufSeqAdr", {BufSeqAdr}, 37b, "BufSeqAdr wrong;*n check BufSeqAdr register.", 2, 1, 4) goto L71
if Stop() goto L71
return
]

//Test72To test:Counter Branch

let Test72() be
[
L72: Start()

//SubTest72.1.0; checks Counter clear and BrCry
{dClrCntr’} = 0
EClock()
{dClrCntr’} = 1
{dBrCry} = 1
EClock()//Should clear counter
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "BufAdrSeq.7 wrong;*n check ClrCntr’ FF, Branch counter, and BufSeqAdr.7 generation gates.", 2, 1) goto L72

//SubTest72.2.n; checks that Counter counts to max
{dIncCntr} = 1
EClock()
for n = 0 to 13 do
[
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "Branch counter*n reached max in too few clocks; check ClrCntr’ FF and Branch counter.", 2, 2, n) goto L72
]
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 0, "Branch counter*n did not reach max in 15 clocks; check BrCry FF and Branch counter.", 2, 2, 14) goto L72

//SubTest72.3.n; checks that IncCntr controls counter
{dIncCntr} = 0
{dClrCntr’} = 0
EClock()
{dClrCntr’} = 1
EClock()//Should clear counter
for n = 0 to 14 do
[
{dIncCntr} = 0
EClock()
{dIncCntr} = 1
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "Branch counter*n not controlled by IncCntr; check IncCntr FF and Branch counter.", 2, 3, n) goto L72
]
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 0, "Branch counter*n not controlled by IncCntr; check IncCntr FF and Branch counter.", 2, 3, 15) goto L72

//SubTest72.4.n; checks Counter load
{dLdCntr’} = 0
EClock()
{dLdCntr’} = 1
EClock()//Should load counter with 14b
for n = 0 to 1 do//Should increment counter to 17b
[
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "Branch counter*n reached max in too few clocks; check LdCntr’ FF and BrCnt.2 FF.", 2, 4, n) goto L72
]
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 0, "Branch counter*n did not reach max in 3 clocks; check Counter load.", 2, 4, 2) goto L72

{dLdCntr’} = 0
{dBrCnt.2} = 1
EClock()
{dLdCntr’} = 1
EClock()//Should load counter with 16b
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "Branch counter*n not loaded with 16b; check LdCntr’ FF and BrCnt.2 FF.", 2, 4, 3) goto L72
EClock()//Should increment counter to 17b
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 0, "Branch counter*n did not reach max in 1 clock; check Counter load.", 2, 4, 4) goto L72

//SubTest72.5.0; checks BrCry control
{dLdCntr’} = 0
{dBrCnt.2} = 1
EClock()
{dLdCntr’} = 1
{dBrCry} = 0
EClock()//Loads counter with 16b
EClock()//Increments counter to 17b
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "Counter carry*n not inhibited by BrCry; check BrCry FF and BufSeqAdr.7 generation gates.", 2, 5) goto L72

if Stop() goto L72
return
]

//Test73To test:Xfer Branch

let Test73() be
[
L73: Start()
{dBrXfer} = 1
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "BufSeqAdr.7 wrong;*n check XferDataS and BufSeqAdr.7 generation gates.", 2, 1) goto L73

EnableDevClk()
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; sets ByteClkEnbl
{dXferTime} = 1
for n = 0 to 16 do//Set XferData
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
EClock()//Should set XferDataS
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 0, "BufSeqAdr.7 wrong;*n check XferDataS and BufSeqAdr.7 generation gates.", 2, 2) goto L73

{dBrXfer} = 0
EClock()
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "XferDataS not*n inhibited by BrXfer; check BrXfer FF and BufSeqAdr.7 generation gates.", 2, 3) goto L73

{dBrXfer} = 1
{dIncDevBufAdr} = 1
EClock()
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; resets XferData
EClock()//Should clear XferDataS
if not Compare("BufSeqAdr.7", {BufSeqAdr.7}, 1, "XferDataS not*n cleared by IncDevBufAdr; check XferDataS FF and IncDevBufAdr inverter.", 2, 4) goto L73

if Stop() goto L73
return
]