//**************************************************************************************
//RDC6.tst
//Device Format Sequencer Control Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{ForSeqAdr: ForSeqAdr.0, ForSeqAdr.1, ForSeqAdr.2, ForSeqAdr.3, ForSeqAdr.4, ForSeqAdr.5, ForSeqAdr.6, ForSeqAdr.7}
//{ForCnt: dForCnt.1, dForCnt.2, dForCnt.3, dForCnt.4}

//**************************************************************************************
//Test61To test:Address Selection

let Test61() be
[
L61: Start()
EnableDevClk()
//SubTest61.1.0; checks initial address loading via SectorMarkSD
OData(DevOpRegLd)//Clears DevOpReg
//Initialize Time Gen
OData(TestRegLd, 405b)//Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 405b)//CyclesDevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets ByteClkEnbl
OData(TestRegLd, 405b)//CyclesDevClk
OData(TestRegLd, 404b)//Cycles DevClk & ByteClk
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; loads starting SeqAdr
if not Compare("ForSeqAdr", {ForSeqAdr}, 201b, "Device Format Sequencer*n initial address wrong; check select gate and ForSeqAdr[0:6].", 2, 1) goto L61
//SubTest61.1.1; checks next address loading
{dSequenceEnd} = 1
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; loads next address
if not Compare("ForSeqAdr", {ForSeqAdr}, 376b, "Device Format Sequencer*n initial address wrong; check select gate and ForSeqAdr[0:6].", 2, 1, 1) goto L61

//SubTest61.1.2; checks initial address loading via SequenceEnd
for n = 0 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr", {ForSeqAdr}, 221b, "Device Format Sequencer*n initial address wrong; check select gate and ForSeqAdr[0:6].", 2, 1, 2) goto L61

if Stop() goto L61
return
]

//Test62To test:Branch Control

let Test62() be
[
L62: Start()
EnableDevClk()
//Initial Branch Counter load of 20b
OData(DevOpRegLd)//Clears DevOpReg
OData(TestRegLd, 405b)//Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 405b)//CyclesDevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets ByteClkEnbl
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; loads starting SeqAdr
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; loads counter

//SubTest62.1.n; checks that Branch Counter reaches max in 15 counts when loaded with 20b
for n = 0 to 13 do
[
for k = 0 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 0, "Format Sequencer*n Branch Counter reached max too soon; check counter load and ForSeqAdr.7.", 2, 1, n) goto L62
]

//SubTest62.1.14; checks that Branch Counter reaches max after 15 counts
for k = 0 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 1, "Format Sequencer*n Branch Counter did not reach max in 15 counts; check counter and ForSeqAdr.7.", 2, 1, 14) goto L62

//SubTest62.2.n; checks that Branch Counter load all bits and counts properly
let cntval = table[ 10b; 4b; 2b; 1b ]
let numcnt = table[ 5; 9; 11; 12 ]
for j = 0 to 3 do
[
let n = j * 100
{ForCnt} = cntval!j
for k = 0 to 7 do//Load initial count
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
for i = 0 to numcnt!j do
[
for k = 0 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 0, "Format Sequencer*n Branch Counter reached max too soon; check counter load and ForSeqAdr.7.", 2, 2, n) goto L62
n = n + 1
]
for k = 0 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 1, "Format Sequencer*n Branch Counter did not reach max in proper count; check counter and ForSeqAdr.7.", 2, 2, n) goto L62
]

//SubTest62.3.n; checks SyncFound Branch
{ForCnt} = 17b
{dSyncTime} = 1
{dBrOnSync} = 1
for k = 0 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 0, "BrOnSync did not*n inhibit ForSeqAdr.7; check BrOnSync FF and ForSeqAdr.7.", 2, 3) goto L62
for k = 0 to 1 do//Generate SyncFound
[
OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
]
if not Compare("ForSeqAdr.7", {ForSeqAdr.7}, 1, "Sync did not*n generate ForSeqAdr.7; check BrOnSync FF and ForSeqAdr.7.", 2, 3, 1) goto L62

if Stop() goto L62
return
]