//**************************************************************************************
//RDC5.tst
//Serializer/Deserializer Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//Test51To test:Dev ← Buffer Data; Shifter; Buffer ← Dev Data

let Test51() be
[
L51: Start()
EnableDevClk()
for n = 0 to 2 do//Generates ByteClk
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClkSource
OData(TestRegLd, 404b)//Cycles DevClkSource
]

//Clear MemBufAdrReg to 0; Load buffer
OData(MemBufAdrLd)
OData(BufDataLd, 1)

{dClrDevOp’} = 0
OData(TestRegLd, 405b)//Generates ByteClk
OData(TestRegLd, 404b)//Generates ByteClk
EClock()//Sets ClrDevOpS’ FF
EClock()//Clear DevBufAdrReg

//Load buffer output register
{dDev←Buf} = 1
EClock()
{dDev←Buf} = 0
EClock()

//Initialize Time Gen
{dClrDevOp’} = 1
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; sets ByteClkEnbl
{dXferTime} = 1
{dDataTime} = 1
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk

//Produce LoadReg for transfer of buffer output register to serializer
for n = 0 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]

//SubTest51.1.n; checks that 1 shifts thru serializer
let wrtdt = 0
for n = 0 to 14 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Write Data", wrtdt, 0, "Write Data not zero;*n check DevInReg, shifter, DevWrtData’ gates, WriteData driver and receiver,*n and Test Idata.", 1, 1, n) goto L51
]
OData(TestRegLd, 403b)//Cycles DevClk; sets RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; sets RdData = 1
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Write Data", wrtdt, 1, "Write Data not one;*n check DevInReg, shifter, DevWrtData’ gates, WriteData driver and receiver,*n and Test Idata.", 1, 1, 15) goto L51

//SubTest51.2.0; checks deserializer input and transfer to buffer
for n = 0 to 7 do//Loads 0/1 pattern into deserializer
[
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
]

//Transfer deserializer output to buffer
{dWriteBuf} = 1
{dClrMemBufAdr’} = 0
EClock()
{dWriteBuf} = 0
{dClrMemBufAdr’} = 1
Clocks()
OData(PrimeIData)//Prime Idata

//Read buffer data and compare
IData(Buf)
if not Compare("Read Data", idt, 125252b, "Read Data incorrect;*n check TestReg, DevRdData FF, DevData MUX, deserializer shifter, DevOutReg.", 2, 2) goto L51

if Stop() goto L51
return
]

//Test52To test:Sync Detector

let Test52() be
[
L52: Start()
EnableDevClk()
//SubTest52.1.n; checks that 12b is recognized as sync pattern
{dSyncTime} = 1
for n = 0 to 3 do//Initialize Time Gen; clear deserializer
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk & ByteClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk

OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 1) goto L52
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 1, 1) goto L52
OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 1, 2) goto L52
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
if not Compare("SyncFound", {SyncFound}, 1, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 1, 3) goto L52

//SubTest52.2.0; checks that SyncFound is not produced when XferTime is true
//Initialize Time Gen
{dXferTime} = 1
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; Sets ByteClkEnbl
OData(TestRegLd, 401b)//Cycles DevClk & ByteClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk

OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 2) goto L52
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 2, 1) goto L52
OData(TestRegLd, 403b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 402b)//Cycles DevClk; RdData = 1
if not Compare("SyncFound", {SyncFound}, 0, "Sync failure;*n check SyncOK comparator and TimeGen.", 2, 2, 2) goto L52
OData(TestRegLd, 401b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 400b)//Cycles DevClk; RdData = 0
if not Compare("SyncFound", {SyncFound}, 0, "SyncFound produced*n when XferTime true; check SyncOK comparator and TimeGen.", 2, 2, 3) goto L52

if Stop() goto L52
return
]

//Test53To test:Sync Time Write Data

let Test53() be
[
L53: Start()
EnableDevClk()
//SubTest53.1.n; checks Write Data pattern = 5b during SyncTime
//Initialize Time Gen
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; sets ByteClkEnbl
{dSyncTime} = 1
{dXferTime} = 1
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk

let wrtdt = 0
for n = 0 to 11 do
[
OData(TestRegLd, 401b)//Cycles DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Sync Data", wrtdt, 0, "SyncTime Data not zero;*n check SyncTime FF, Time Gen, and DevWrtData’ gates.", 2, 1, n) goto L53
]
OData(TestRegLd, 401b)//Cycles DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Sync Data", wrtdt, 1, "SyncTime Data not one;*n check SyncTime FF, Time Gen, and DevWrtData’ gates.", 2, 1, 12) goto L53
OData(TestRegLd, 401b)//Cycles DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Sync Data", wrtdt, 0, "SyncTime Data not zero;*n check SyncTime FF, Time Gen, and DevWrtData’ gates.", 2, 1, 13) goto L53
OData(TestRegLd, 401b)//Cycles DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Sync Data", wrtdt, 1, "SyncTime Data not one;*n check SyncTime FF, Time Gen, and DevWrtData’ gates.", 2, 1, 14) goto L53

//SubTest53.2.n; checks that SyncTime inhibits pattern
//Initialize Time Gen
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk; sets ByteClkEnbl
{dSyncTime} = 0
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk

for n = 0 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
IData(Test)
wrtdt = (idt & 2b) rshift 1
if not Compare("Sync Data", wrtdt, 0, "SyncTime Data not zero;*n check SyncTime FF and DevWrtData’ gates.", 2, 2, n) goto L53
]

if Stop() goto L53
return
]


//Test54To test: Compare Logic

let Test54() be
[
L54: Start()
EnableDevClk()
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
for n = 0 to 6 do//Loads 0/1 pattern into deserializer
[
OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
]
OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1
{dDataTime} = 1
OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0

//SubTest54.1.n; checks NonComp with RdData = 0
OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 0, "NonCompS not false;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 1) goto L54

OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 1, "NonCompS not true;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 1, 1) goto L54

OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 1, "NonCompS not true;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 1, 2) goto L54

OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 0, "NonCompS not false;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 3) goto L54

//SubTest54.2.n; checks NonComp with RdData = 0
{dDataTime} = 0
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
for n = 0 to 6 do//Loads 1/0 pattern into deserializer
[
OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1
]
OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
{dDataTime} = 1
OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1

OData(TestRegLd, 407b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 0
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 1, "NonCompS not true;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 2) goto L54

OData(TestRegLd, 407b)//Cycles DevClk; RdData = 1
OData(TestRegLd, 406b)//Cycles DevClk; RdData = 1
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 1, "NonCompS not true;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 2, 1) goto L54

OData(TestRegLd, 405b)//Cycles DevClk; RdData = 0
OData(TestRegLd, 404b)//Cycles DevClk; RdData = 0
EClock()//Sets NonCompS
if not Compare("NonComp", {NonCompS}, 0, "NonCompS not false;*n check Compare gate, NonCompFF, and NonCompS FF.", 2, 2) goto L54

if Stop() goto L54
return
]