//**************************************************************************************
//RDC4.tst
//Data Buffer Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{BufAdr: BufAdr.0, BufAdr.1, BufAdr.2, BufAdr.3, BufAdr.4, BufAdr.5, BufAdr.6}
//{Iaddr: Iaddr.0, Iaddr.1, Iaddr.2, Iaddr.3, Iaddr.4, Iaddr.5, Iaddr.6, Iaddr.7}

//**************************************************************************************
//Test41To test:DevBufAdr Register

let Test41() be
[
L41: Start()
{BufAdr} = ###
EnableDevClk()
for n = 0 to 2 do//Generates ByteClk
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClkSource
OData(TestRegLd, 404b)//Cycles DevClkSource
]

//SubTest41.1; checks that DevBufAdrReg is cleared
{dClrDevOp’} = 0
OData(TestRegLd, 405b)//Generates ByteClk
OData(TestRegLd, 404b)//Generates ByteClk
EClock()//Sets ClrDevOpS’ FF
EClock()//Clears DevBufAdrReg
if not Compare("DevBufAdr", {BufAdr}, 0b, "DevBufAdrReg not*n cleared; check ClrDevOp’ FF and ClrDevOpS’ FF.", 2, 1) goto L41

//SubTest41.2.n; checks that DevBufAdrReg increments
{dClrDevOp’} = 1
OData(TestRegLd, 405b)//Generates ByteClk
OData(TestRegLd, 404b)//Generates ByteClk
{dIncDevBufAdr} = 1
EClock()//Sets IncDevBufAdr; LoadsBufAdrReg
EClock()
for n = 0 to 175b do
[
if not Compare("DevBufAdr", {BufAdr}, n, "DevBufAdrReg*n has wrong value; check IncDevBufAdr FF, DevBufAdrReg, and BufAdrReg.", 2, 2, n) goto L41
EClock()//Increments DevBufAdrReg
EClock()//Increments DevBufAdrReg
]
if not Compare("DevBufAdr", {BufAdr}, 176b, "DevBufAdrReg*n has wrong value; check IncDevBufAdr FF, DevBufAdrReg, and BufAdrReg.", 2, 2, 176) goto L41
EClock()//Increments DevBufAdrReg
{dIncDevBufAdr} = 0
EClock()//Increments DevBufAdrReg

//SubTest41.3.n; checks again that DevBufAdrReg clears
if not Compare("DevBufAdr", {BufAdr}, 177b, "DevBufAdrReg*n has wrong value; check IncDevBufAdr FF, DevBufAdrReg, and BufAdrReg.", 2, 3) goto L41
{dClrDevOp’} = 0
OData(TestRegLd, 405b)//Generates ByteClk
OData(TestRegLd, 404b)//Generates ByteClk
EClock()//Sets ClrDevOpS’ FF
EClock()//Clear DevBufAdrReg
if not Compare("DevBufAdr", {BufAdr}, 0, "DevBufAdrReg*n not cleared; check IncDevBufAdr FF, DevBufAdrReg, and BufAdrReg.", 2, 3, 1) goto L41

if Stop() goto L41
return
]

//Test42To test: MemBufAdr Register

let Test42() be
[
L42: Start()
EnableDevClk()
for n = 0 to 2 do//Generates ByteClk
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClkSource
OData(TestRegLd, 404b)//Cycles DevClkSource
]
let adrval = table[ 0b; 200b; 100b; 40b; 20b; 10b; 4b; 2b ]

//SubTest42.1.n; checks MemBufAdrReg load
for n = 0 to 7 do
[
OData(MemBufAdrLd, adrval!n)
{IValid’} = 0
EClock()//Sets IMeF
{IValid’} = 1
let bfad = {BufAdr} lshift 1
if not Compare("MemBufAdr", bfad, adrval!n, "*nMemBufAdrReg not loaded properly; check MemBufAdrLd’, OutD[08:15],*n MemBufAdrReg, and BufAdrReg.", 1, 1, n) goto L42
]

//SubTest42.2.n; checks that MemBufAdrReg is cleared
OData(MemBufAdrLd, 376b)
{IValid’} = 0
EClock()//Sets IMeF
{IValid’} = 1
let bfad = {BufAdr} lshift 1
if not Compare("MemBufAdr", bfad, 376b, "*nMemBufAdrReg not loaded properly; check MemBufAdrLd’, OutD[08:15],*n MemBufAdrReg, and BufAdrReg.", 1, 2) goto L42
{dClrMemBufAdr’} = 0
EClock()//Sets ClrMemBufAdr’ FF
EClock()//Clears MemBufAdrReg
{dClrMemBufAdr’} = 1
{IValid’} = 0
EClock()//Sets IMeF
{IValid’} = 1
if not Compare("MemBufAdr", {BufAdr}, 0b, "*nMemBufAdrReg not cleared; check SectorWake’ FF and SectorWakeS’ FF.", 2, 2, 1) goto L42

//SubTest42.3.n; checks that MemBufAdrReg increments
OData(MemBufAdrLd, 1b)//Insures LSB is working
OData(BufDataLd)//Sets MemUsesBuf FF
for n = 1 to 177b do
[
{IValid’} = 0
EClock()//Sets IMeF
if not Compare("MemBufAdr", {BufAdr}, n, "MemBufAdrReg*n has wrong value; check MemUsesBuf Gate and Driver, MemBufAdrReg,*n and BufAdrReg.", 1, 3, n) goto L42
{IValid’} = 1
EClock()//Resets IMeF
IData(Buf)// Increments MemBufAdrReg
OData(BufDataLd)// Increments MemBufAdrReg
]

if Stop() goto L42
return
]

//Test43To test:Buffer Data Path to and from Processor

let Test43() be
[
L43: Start()
EnableDevClk()
for n = 0 to 2 do//Generates ByteClk
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClkSource
OData(TestRegLd, 404b)//Cycles DevClkSource
]
//Clear MemBufAdrReg to 0
OData(MemBufAdrLd)

//Check all data combinations in all buffer addresses
for i = 0 to 17b do
[
let baseval = (((i lshift 4 + i) lshift 4 + i) lshift 4 + i)
OData(BufDataLd, baseval, 256, 10421b)
OData(PrimeIData)
for n = 0 to 255 do
[
IData(Buf)

//SubTest43.1.n; checks Buffer Idata parity
if not Compare("Err", ParErr, 0, "Buf Data parity error;*n check BufParIn’ gate, Buffer Parity RAM, BufIdataPar FF, and Idata.16 MUX.", 2, 1, n) goto L43

//SubTest43.2.n; checks Buffer data content
if not Compare("Buffer Data", idt, baseval, "Buf Data wrong; check Buffer RAMs, BufWE’ gate, and Buffer Idata register.", 2, 2, n) goto L43
baseval = baseval + 10421b
]
]

if Stop() goto L43
return
]