//**************************************************************************************
//RDC3.tst
//Sequence Address Generator, DevOp Register, and Seek Control Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{SeqAdr: ForSeqAdr.0, ForSeqAdr.1, ForSeqAdr.2, ForSeqAdr.3}

//**************************************************************************************
//Test31To test:Sequence Address Generation

let Test31() be
[
L31: Start()
let opval = table[ 0b; 200b; 100b; 300b; 140b; 120b; 130b; 104b; 102b; 101b; 377b ]
let adrval1 = table[ 10b; 11b; 12b; 17b; 01b; 11b; 12b; 17b; 02b; 11b; 12b; 17b; 10b; 11b; 12b; 17b; 02b; 03b; 12b; 17b; 02b; 04b; 12b; 17b; 02b; 04b; 12b; 17b; 02b; 11b; 05b; 17b; 02b; 11b; 06b; 17b; 02b; 11b; 07b; 17b; 10b; 11b; 12b; 17b ]
let adrval2 = table[ 10b; 11b; 12b; 13b ]
EnableDevClk()
{dSequenceEnd} = 1
for k = 0 to 2 do//Clear NonComp
[
OData(TestRegLd, 405b)//Sets SectorMark; Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]

//SubTest31.1.n; checks SeqAdr generation with Abort false
let n = 0//Index for adrval table
for i = 0 to 10 do
[
OData(DevOpRegLd, opval!i)
OData(ErrReset)//Clears Abort if set
{dSequenceEnd} = 0
for k = 0 to 3 do//Load SeqCnt
[
OData(TestRegLd, 405b)//Sets SectorMark; Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]
OData(TestRegLd, 401b)//Resets SectorMark; Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; Load SeqCnt
//SeqAdr is checked via ForSeq[0:3]
if not Compare("SeqAdr", {SeqAdr}, adrval1!n, "SeqAdr wrong; check*n DevOpReg, holding reg(S174), SeqCnt, SequenceEnd FF, ForSeqAdr register,*n Abort control, and SeqAdr generator PROM.", 1, 1, n) goto L31
n = n + 1
{dSequenceEnd} = 1
OData(TestRegLd, 401b)//Cycles DevClk & ByteClk
OData(TestRegLd, 400b)//Cycles DevClk & ByteClk; resets ByteClkEnbl
for j = 0 to 2 do
[
//Produces ByteClk; Inc SeqCnt; transfers SeqAdr to ForSeqAdr
for k = 0 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClkSource - 1
OData(TestRegLd, 400b)//Cycles DevClkSource - 0
]
if not Compare("SeqAdr", {SeqAdr}, adrval1!n, "SeqAdr wrong; check*n DevOpReg, holding reg(S174), SeqCnt, SequenceEnd FF, ForSeqAdr register,*n Abort control, and SeqAdr generator PROM.", 1, 1, n) goto L31
n = n + 1
]
]

//SubTest31.2.n; checks Abort control
{OFault’} = 0
OData(DevOpRegLd)//Sets OFaultF
EClock()//Sets Abort
for n = 0 to 3 do//Produces ByteClk; Inc SeqCnt twice
[
for k = 0 to 15 do//Produces ByteClk; Inc SeqCnt
[
OData(TestRegLd, 401b)//Cycles DevClkSource - 1
OData(TestRegLd, 400b)//Cycles DevClkSource - 0
]
if not Compare("SeqAdr", {SeqAdr}, adrval2!n, "SeqAdr wrong with Abort true;*n check SeqCnt and Abort control.", 2, 2, n) goto L31
]
OData(ErrReset)//Resets Abort

if Stop() goto L31
return
]


//Test32To test:Seek Control

let Test32() be
[
L32: Start()
EnableDevClk()

//SubTest32.1.n; checks Step generation
OData(DevOpRegLd, 3000b)
for n = 0 to 6 do
[
{Phase1Next’} = 0
EClock()
{Phase1Next’} = 1
IData(Test)
let stp = (idt & 40000b) rshift 14
if not Compare("Step", stp, 0, "Step not zero; check DevOpReg,*n Seek counter, Step’ driver, and Test Idata.02.", 2, 1, n) goto L32
]
for n = 7 to 13 do
[
{Phase1Next’} = 0
EClock()
{Phase1Next’} = 1
IData(Test)
let stp = (idt & 40000b) rshift 14
if not Compare("Step", stp, 1, "Step not set; check DevOpReg,*n Seek counter, Phase1Next gates, Step’ driver, and Test Idata.02.", 2, 1, n) goto L32
]
{Phase1Next’} = 0
EClock()
{Phase1Next’} = 1
IData(Test)
let stp = (idt & 40000b) rshift 14
if not Compare("Step", stp, 0, "Step not zero; check DevOpReg,*n Seek counter, Step’ driver, and Test Idata.02.", 2, 1, 14) goto L32

//SubTest32.2.n; checks Direction bit and ClrDevOpS
OData(DevOpRegLd)
IData(Test)
let dir = (idt & 20000b) rshift 13
if not Compare("Direction", dir, 0, "Direction not zero;*n check DevOpReg, Direction’ driver, and Test Idata.02.", 2, 2) goto L32
OData(DevOpRegLd, 3000b)
IData(Test)
let dir = (idt & 20000b) rshift 13
if not Compare("Direction", dir, 1, "Direction not set;*n check DevOpReg, Direction’ driver, and Test Idata.02.", 2, 2, 1) goto L32
{dClrDevOp’} = 0
for n = 0 to 2 do//Generates ByteClk
[
OData(TestRegLd, 405b)//Sets SectorMark; Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
]
EClock()//Resets ClrDevOpClr’
IData(Test)
let dir = (idt & 20000b) rshift 13
if not Compare("Direction", dir, 0, "Direction set when*n ClrDevOpS should be true; check DevOpReg, ClrDevOp’ FF, ClrDevOpS’ FF,*n Direction’ driver, and Test Idata.02.", 1, 2, 2) goto L32

if Stop() goto L32
return
]