//**************************************************************************************
//RDC2b.tst
//Even More Device Simulator & Interface Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{IAddr: Iaddr.0, Iaddr.1, Iaddr.2, Iaddr.3, Iaddr.4, Iaddr.5, Iaddr.6, Iaddr.7}
//{OData: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07, Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{TimeGen: ByteClkEnbl, SyncFound, LoadReg, XferData}

//**************************************************************************************
//Test24To test: Sector00

let Test24() be
[
L24: Start()
EnableDevClk()

//SubTest24.1.0; checks that IndexMark sets Sector00
for n = 0 to 2 do
[
OData(TestRegLd, 411b)//Sets IndexMark, & DevClk
OData(TestRegLd, 410b)//Cycles DevClk
]
EClock()
IData(Status)
let sect00 = (idt & 200b) rshift 7
if not Compare("Sector00S", sect00, 1, "Sector00S not set;*n check ByteClk, Sector00 FF, Sector00 FF set gates, Sector00 inverter, Sector00S,*n & Status Idata MUX.", 1, 1) goto L24

//SubTest24.2.0; checks that Sector00 remains set with IndexMark & SectorMark = 0
for n = 0 to 15 do//Cycles ByteClk
[
OData(TestRegLd, 401b)//Sets IndexMark, & DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
EClock()
IData(Status)
sect00 = (idt & 200b) rshift 7
if not Compare("Sector00S", sect00, 1, "Sector00S did not remain set;*n check Sector00 FF set gates,.", 2, 2) goto L24

//SubTest24.3.0; checks that Sector00 is reset at SectorMark
for n = 0 to 2 do
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk
]
EClock()
IData(Status)
sect00 = (idt & 200b) rshift 7
if not Compare("Sector00S", sect00, 0, "Sector00S not reset; check*n Sector00 FF set gates.", 2, 3) goto L24
if Stop() goto L24
return
]

//Test25To test: ReadGate; DevClkFeed control

let Test25() be
[
L25: Start()
EnableDevClk()

//SubTest25.1.0; Checks that ReadGate is initially reset
IData(Test)
let rdgt = (idt & 10b) rshift 3
if not Compare("ReadGate", rdgt, 0, "ReadGate not initially reset;*n check ReadGate FF, ReadGateD’ gate, & Test Idata.", 2, 1) goto L25

//SubTest25.2.0; Checks that ReadGate is set
{dReadGate} = 1
for n = 0 to 2 do//First cycle sets SectorMarkSD; second sets ByteClkEnbl
[
OData(TestRegLd, 405b)//Sets SectorMark & DevClk
OData(TestRegLd, 404b)//Cycles DevClk
]
IData(Test)
rdgt = (idt & 10b) rshift 3
if not Compare("ReadGate", rdgt, 1, "ReadGate not set;*n check ReadGate FF, ReadGateD’ gate, & Test Idata.", 2, 2) goto L25

//SubTest25.3.0; Checks that ReadGate is reset
{dReadGate} = 0
OData(TestRegLd, 401b)//Resets SectorMark; sets DevClk
OData(TestRegLd, 400b)//Cycles DevClk
IData(Test)
rdgt = (idt & 10b) rshift 3
if not Compare("ReadGate", rdgt, 0, "ReadGate not reset;*n check ReadGate FF, ReadGateD’ gate.", 2, 3) goto L25

//SubTest25.4.n; checks DevClkFeed control
for n = 0 to 2 do
[
OData(TestRegLd, 401b)//Sets DevClkSource
OData(TestRegLd, 400b)//Cycles DevClkSource
if not Compare("TimeGen Output", {TimeGen}, 10b, "ByteClk produced*n before 3 DevClkSource cycles; check DevClkFeed enable counter.", 2, 4, n) goto L25
]
for n = 3 to 9 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen reached*n non-zero state in too few clocks; check DevClkFeed enable counter.", 2, 4, n) goto L25
]
OData(TestRegLd, 401b)//Sets DevClk
OData(TestRegLd, 400b)//Cycles DevClk and ByteClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "ByteClkEnbl not*n produced after 12 DevClkSource cycles; check DevClkFeed enable counter.", 2, 4, 10) goto L25
for n = 11 to 17 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen reached*n non-zero state in too few clocks; check DevClkFeed enable counter.", 2, 4, n) goto L25
]
OData(TestRegLd, 401b)//Sets DevClk
OData(TestRegLd, 400b)//Cycles DevClk and ByteClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "ByteClkEnbl not*n produced after 8 DevClkSource cycles; check DevClkFeed enable counter.", 2, 4, 18) goto L25

//SubTest25.5.0; Checks that SectorMarkSP andReadGate set Abort
{dReadGate} = 1
for n = 0 to 1 do//Generate ByteClk; Set SectorMarkSP and ReadGate
[
OData(TestRegLd, 405b)
OData(TestRegLd, 404b)
]
EClock()//Should set Abort
if not Compare("Abort", {Abort}, 1, "Abort not set by ReadGate*n and SectormarkSP; check Abort set gates, ReadGate, and SectorMarkSP.", 2, 5) goto L25

if Stop() goto L25
return
]

//Test26To test: WriteGate

let Test26() be
[
L26: Start()
EnableDevClk()
for n = 0 to 1 do//Cycles ByteClk
[
OData(TestRegLd, 405b)//Cycles DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets ByteClkEnbl
]
//SubTest26.1.0; checks that SectorMarkSD resets WriteGate
let wrtgt = 0
{dWriteGate} = 1
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
IData(Test)
wrtgt = (idt & 4b) rshift 2
if not Compare("WriteGate", wrtgt, 0, "WriteGate not reset; check*n WriteGateEnbl, WriteGate FF’s, WriteGateD’ gate, and Test Idata.", 2, 1) goto L26

//SubTest26.2.1; checks that WriteGateEnbl sets WriteGate
for i = 0 to 1 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
IData(Test)
wrtgt = (idt & 4b) rshift 2
if not Compare("WriteGate", wrtgt, 1, "WriteGate not set by*n WriteGateEnbl; check WriteGateEnbl, WriteGate FF’s, WriteGateD’ gate, and Test Idata.", 2, 2, 1) goto L26

//SubTest26.2.2; checks that DevSelOK inhibits WriteGateD’
OData(DrHdRegLd, 60)//Resets DevSelOK
IData(Test)
wrtgt = (idt & 4b) rshift 2
if not Compare("WriteGate", wrtgt, 0, "WriteGate not inhibited*n by DevSelOK; check WriteGateD’ gate.", 2, 2, 2) goto L26

//SubTest26.2.3; Reset and check WriteGate
OData(TestRegLd, 605b)//Sets Ready, SectorMark, & DevClkSource
OData(TestRegLd, 604b)//Cycles DevClkSource; sets SectorMarkSD
OData(TestRegLd, 204b)//Resets TestMode; First EdgeClk sets SectorMarkSP
for n = 0 to 15 do [ EClock() ]//Sets DevSelOK
{dWriteGate} = 1
for i = 0 to 2 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
IData(Test)
wrtgt = (idt & 4b) rshift 2
if not Compare("WriteGate", wrtgt, 1, "WriteGate not enabled*n by DevSelOK; check WriteGate generation.", 2, 2, 3) goto L26

//SubTest26.2.4; checks that WriteGateEnbl resets WriteGate
{dWriteGate} = 0
for n = 0 to 8 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
]
IData(Test)
wrtgt = (idt & 4b) rshift 2
if not Compare("WriteGate", wrtgt, 0, "WriteGate not reset by*n WriteGateEnbl = 0; check WriteGateEnbl, WriteGate FF’s, WriteGateD’ gate,*n and Test Idata.", 1, 2, 4) goto L26

if Stop() goto L26
return
]


//Test27To test:FaultClear’

let Test27() be
[
L27: Start()
//SubTest27.1.0; checks that FaultClear is generated
IData(Test)
let clr = (idt & 10000b) rshift 12
if not Compare("FaultClear", clr, 0, "FaultClear set; check FaultClear’ gate, WrtFltClr FF, and Test Idata.03.", 2, 1) goto L27
SetCaddr()
{IAddr} = (Caddr lshift 4) % 2b
{AdvancePipe’} = 0
EClock()
{AdvancePipe’} = 1
{MC2StartXport} = 1
EClock()
{MC2StartXport} = 0
{OValid’} = 0
{OData} = 1b
EClock()
{OValid’} = 1
IData(Test)
let clr = (idt & 10000b) rshift 12
if not Compare("FaultClear", clr, 1, "FaultClear not set; check FaultClear’ gate, WrtFltClr FF, and Test Idata.03.", 2, 1, 1) goto L27
IData(Test)
let clr = (idt & 10000b) rshift 12
if not Compare("FaultClear", clr, 0, "FaultClear set; check FaultClear’ gate, WrtFltClr FF, and Test Idata.03.", 2, 1, 2) goto L27

if Stop() goto L27
return
]