//**************************************************************************************
//RDC2a.tst
//More Device Simulator & Interface Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 12, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//To define bus structure
//{TimeGen: ByteClkEnbl, SyncFound, LoadReg, XferData}

//**************************************************************************************
//Test23To test:Timing Gen; ByteClk

let Test23() be
[
L23: Start()
EnableDevClk()

//SubTest23.1.n; Checks that ByteClkEnbl is generated when SectorMarkSD is true
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
for n = 0 to 7 do
[
OData(TestRegLd, 405b)//Sets SectorMark, & DevClk
OData(TestRegLd, 404b)//Cycles DevClk; sets SectorMarkSD
if not Compare("ByteClkEnbl", {ByteClkEnbl}, 1, "ByteClkEnbl not set*n when SectorMarkSD is true; check Time Gen PROM inputs and outputs,*n and Time Gen register.", 1, 1, n) goto L23
]

//SubTest23.2.n; checks Time Gen sequencing, XferTime = 0, SyncTime = 0
OData(TestRegLd, 401b)//Cycles DevClk; resets SectorMark
OData(TestRegLd, 400b)//Cycles DevClk; resets SectorMarkSD
for n = 0 to 6 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen output*n wrong for state n; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 2, n) goto L23
]

OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "Time Gen output*n wrong for state 7; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 2, 7) goto L23

for n = 8 to 14 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen output*n wrong for state n; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 2, n) goto L23
]

OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "Time Gen output*n wrong for state 15; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 2, 15) goto L23

//SubTest23.3.n; checks Time Gen sequencing, XferTime = 1, SyncTime = 0
{dXferTime} = 1
OData(TestRegLd, 405b)//Sets SectorMark, & DevClkSource
OData(TestRegLd, 404b)//Cycles DevClkSource; sets SectorMarkSD

OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "Time Gen output*n wrong for state 7; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 3) goto L23

for n = 1 to 7 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen output*n wrong for state n; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 3, n) goto L23
]

OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 10b, "Time Gen output*n wrong for state 7; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 3, 8) goto L23

for n = 9 to 15 do
[
OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 00b, "Time Gen output*n wrong for state n; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 3, n) goto L23
]

OData(TestRegLd, 401b)//Cycles DevClk
OData(TestRegLd, 400b)//Cycles DevClk
if not Compare("TimeGen Output", {TimeGen}, 13b, "Time Gen output*n wrong for state 15; check Time Gen PROM inputs and outputs, and Time Gen register.", 2, 3, 16) goto L23

if Stop() goto L23
return
]