//**************************************************************************************
//RDC2.tst
//Device Simulator & Interface Tests
//By J. F. CameronJuly 11, 1978
//Last modified by J. F. CameronJune 13, 1980
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "RDC.d"

//**************************************************************************************
//Test21To test:Dr/Hd Select; Drive Interface; Idata (TestGroup)

let Test21() be
[
L21: Start()
let odataval = table[ 0b; 20b; 40b; 60b; 10b; 4b; 2b; 1b ]
let drhdval = table[ 200b; 100b; 40b; 20b; 210b; 204b; 202b; 201b ]

//Checks loading of each bit of Dr/HdRegister,
// associated interface drivers, and Idata Test Group
for n = 0 to 7 do
[
OData(DrHdRegLd, odataval!n)
IData(Test)

//SubTest21.1.n; Checks Idata parity
if not Compare("Err", ParErr, 0, "Test Group Idata parity error;*n check Idata.16 MUX, and IMuxPar generator.", 2, 1, n) goto L21

//SubTest21.2.n; Checks Drive/Head Selection
let drhd = (idt & 7760b) rshift 4
if not Compare("Drive/Head Select", drhd, drhdval!n, "Drive/Head Select*n error; check Dr/Hd Register, interface drivers, and Idata Test Group(Logic Dwgs., p.16).", 2, 2, n) goto L21
]

//SubTest21.3.0; Checks reset of Dr/HdReg
OData(GeneralReset)
IData(Test)
let drhd = (idt & 7760b) rshift 4
if not Compare("Drive/Head Select", drhd, 200b, "Drive/Head Select*n not reset; check Dr/Hd Register.", 2, 3) goto L21

if Stop() goto L21
return
]


//Test22To test: Idata(Status); Test Register; Sector Mark; DevSelOK; Dev Clock

let Test22() be
[
L22: Start()

//SubTest22.1.n; Checks Status Idata and Test Register Clear
OData(DrHdRegLd, 40b)
OData(DrHdRegLd, 00b)//Clears DevSelOK
OData(TestRegLd, 400b)//Clears Test Register; sets TestMode
EClock()//Clears processor sync’ed signals
IData(Status)
//SubTest22.1.0; Checks Idata parity
if not Compare("Err", ParErr, 0, "Status Group Idata parity error;*n check Idata.16 MUX, and IMuxPar generator.", 2, 1) goto L22
//SubTest22.1.1; Checks Status Idata & Test Register clear
let mskstat = idt & 177b
if not Compare("Status", mskstat, 0b, "Status error;*n check Idata Register, Idata MUXs, or failed bit source.", 2, 1, 1) goto L22

//SubTest22.2.n; Checks Status Idata, Test Register Load, and DevClk Generation
OData(TestRegLd, 520b)//Sets TestMode, WriteFault, SeekComp (active low), & Track00
EClock()//Sets processor sync’ed signals & Abort
//SubTest22.2.0; Checks Idata parity
IData(Status)
if not Compare("Err", ParErr, 0, "Status Group Idata parity error;*n check Idata.16 MUX, and IMuxPar generator.", 2, 2) goto L22
//SubTest22.2.1; Checks Status Idata & Test Register load
let mskstat = idt & 177b
if not Compare("Status", mskstat, 102b, "Status error;*n check Idata Register, Idata MUXs, or failed bit source.", 2, 2, 1) goto L22
//SubTest22.2.2 & 3; Check DevClk generation
IData(Test)
let clk = idt & 1b
if not Compare("TWriteClock", clk, 0, "TwriteClock true;*n check Test Register DevClkSource, DevClkFeed & DevClk’ gates, WriteClock driver,*n TWriteClock’ receiver, and Test Idata.15", 1, 2, 2) goto L22
EnableDevClk()
OData(TestRegLd, 401b)//Sets DevClkSource
IData(Test)
let clk = idt & 1b
if not Compare("TWriteClock", clk, 1, "TwriteClock not true;*n check Test Register DevClkSource, DevClkFeed & DevClk’ gates, WriteClock driver,*n TWriteClock’ receiver, and Test Idata.15", 1, 2, 3) goto L22

//SubTest22.3.n; Checks that Ready & SectorMarkSP control DevSelOK counter
OData(TestRegLd, 000b)//Clears Test Register
for n = 0 to 7 do
[
IData(Status)//Cycles EdgeClk twice; reads after first
mskstat = (idt & 20b) rshift 4
//Checks that DevSelOK counter is inhibited
if not Compare("DevSelOK", mskstat, 0, "DevSelOK set;*n check DevSelOK counter.", 2, 3, n) goto L22
]
IData(Status)//Cycles EdgeClk twice; reads after first
mskstat = (idt & 20b) rshift 4
//SubTest22.3.8; Checks that DevSelOK counter is inhibited
if not Compare("DevSelOK", mskstat, 0, "DevSelOK set after 15*n clocks; check DevSelOK counter enable.", 2, 3, 8) goto L22

//DevClk must work to set SectorMarkSD
OData(TestRegLd, 605b)//Sets Ready, SectorMark, & DevClkSource
OData(TestRegLd, 604b)//Cycles DevClkSource; sets SectorMarkSD
OData(TestRegLd, 204b)//Resets TestMode; First EdgeClk sets SectorMarkSP
for n = 9 to 14 do
[
IData(Status)//Cycles EdgeClk twice; reads after first
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 0, "DevSelOK set with*n less than 15 clocks; check DevSelOK counter on logic dwg., p.14.", 2, 3, n) goto L22
]
//SubTest22.3.15; Checks that DevSelOK counter is enabled
IData(Status)//Cycles EdgeClk twice; reads after first
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 1, "DevSelOK not set after 15*n clocks; check DevSelOK counter and SectorMarkSP.", 2, 3, 15) goto L22

//SubTest22.4.0; Checks that WriteFault resets DevSelOK
OData(TestRegLd, 500b)//Sets TestMode & WriteFault
EClock()//Clears DevSelOK
OData(TestRegLd, 000b)//Resets TestMode & WriteFault
IData(Status)//Cycles EdgeClk twice; reads after first
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 0, "DevSelOK not reset by*n WriteFault; check DevSelOK counter and load gate.", 2, 4) goto L22

//SubTest22.5.n; Checks that Dr/HdRegLd resets DevSelOK,
// and that IndexMark produces SectorMarkSD
let dev = table[ 20b; 60b; 40b; 0b ]
OData(DrHdRegLd)
for n = 0 to 3 do
[
OData(TestRegLd, 611b)//Sets Ready, IndexrMark, & DevClkSource
OData(TestRegLd, 610b)//Cycles DevClkSource; sets SectorMarkSD
OData(TestRegLd, 210b)//Resets TestMode
for i = 0 to 15 do [ EClock() ]//Sets DevSelOK
IData(Status)
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 1, "DevSelOK not enabled by*n IndexMark; check SectorMarkSD.", 2, 5, n) goto L22
OData(DrHdRegLd, dev!n)
IData(Status)
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 0, "DevSelOK not reset by*n Dr/HdRegLd with Dev Num. change; check DevSelOK counter and load gate.", 2, 5, n) goto L22
]

//SubTest22.6.0; Checks that Reset resets DevSelOK,
for n = 0 to 15 do [ EClock() ]//Sets DevSelOK
OData(GeneralReset)
IData(Status)
mskstat = (idt & 20b) rshift 4
if not Compare("DevSelOK", mskstat, 0, "DevSelOK not reset by Reset;*n check DevSelOK counter and load gate.", 2, 6) goto L22

//SubTest22.7.0; Checks that OFaultF is in Status
for i = 0 to 15 do [ EClock() ]//Sets DevSelOK
{OFault’} = 0
OData(DevOpRegLd)
IData(Status)
mskstat = idt & 1b
if not Compare("OFaultF", mskstat, 1, "OFaultF is not in Status;*n check Status MUX.", 2, 7) goto L22

//SubTest22.8.n; Checks that OFault controls Abort
Start()
{OFault’} = 0
OData(DevOpRegLd)//Sets OFaultF
EClock()//Sets Abort
if not Compare("Abort", {Abort}, 1, "Abort not set by OFault;*n check OFault receiver, OFaultF, or Abort set gates.", 2, 8) goto L22
{OFault’} = 1
OData(ErrReset)
if not Compare("Abort", {Abort}, 0, "Abort not reset by RstAbrt/Err;*n check RstAbrt/Err gates or Abort FF.", 2, 8, 1) goto L22

if Stop() goto L22
return
]