//**************************************************************************************
//*** UTVFC6b.TST
//*** Rev. H                                               May 29.1979
//*** Rev. F                                               February 13,1979
//*** V. Vysin                                             
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData0: Odata.00, Odata.01, Odata.02, Odata.03}
//{OData1: Odata.04, Odata.05, Odata.06, Odata.07}
//{OData2: Odata.08, Odata.09, Odata.10, Odata.11}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{T0: T0D0, T0D1, T0D2, T0D3}
//{T1: T1D0, T1D1, T1D2, T1D3}
//{T2: T2D0, T2D1, T2D2, T2D3}
//{T3: T3D0, T3D1, T3D2, T3D3}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}

// to test the Cursor Memory and associated hardware

let Test63() be
[
   Start()
   // we must ensure that the memory is empty @ addr.0
   //{CTask}=#0 
   //SetCAddr(#17) ;   //allimportant;mustrestore MyTask &ICompar
   Compare("MyTask",{MyTask},1,"no chance ",01)
   
   Switch()               // to be sure ControlPhase =0
   NClk(1)

   OddLine()                    // to write the even buffer
   ClearNBlock()
   XeroData()
   WriteAll()

   let i=0
   S2 : unless i eq 2 do
   [
       for a= 0 to 31 do
       [
          for b= 0 to 7 do         //b three bits lsb address
          [
             {ODataL}= 32+ 4*b; //32 to block C0Shift,
             {ODataM}= 3+8*a  ;    // this leaves CoEnbl =0
             ClkCur()
             Switch()     
             NClko(#20)  // PBlank=1,DisablCurs' is low 
             NClk(2)  // the first one also makes BlankTerm=1
             {OData3}=3*(1-(b+i) rem 2) + 12*((b+i) rem 2)
             CurWri()
          ]
// This has written the cursor as follys ; in all lines
//  #3,#14,#3,#14,......   in the first pass ;
// #14,#3,#14,#3, .......... will be written  in the second pass.
// We shall read it back now ..

          {ODataM}=7+8*a ;   //C0Enbl bit =1
          {ODataL}=#177 ;     // (address= -32)C0BitPos0&1=1    
          ClkCur()
          Switch()     
          NClko(#160)  // PBlank=1,both BckGnds are high 
           //enables load in the counter-DisablCurs=lo
          NClk(1)   //loads BlankTerm=1,loads nibble counter w.-32   
          NClk(1)           // loads CoEnbl=0, DisablCurs' still 0
          Switch()     
          NClko(#140)  // PBlank=0,both BckGnds are high 
                            // makes DisablCurs'=high(enables ctng)
          NClk(33)        // counts up to 0,C0Shift becomes 1
          NClk(1)           // loads cursor register
          Compare("This outputT0 ",{T0},0,"  ",1,a )
          Compare("This outputT1 ",{T1},0," ",2,a )
          for n=0 to 7 do
          [
              let r = 8*i+n
              NClk(1)       // loads T0,T1
              Compare("T0  ",{T0}, 3*(1-(n+i) rem 2) + 12*((n+i) rem 2),"NOW, it should have worked",3,r) 
              Compare("T1  ",{T1}, 3*(1-(n+i) rem 2) + 12*((n+i) rem 2),"NOW, it should have worked",4,r) 
          ]
       ]
       i = i+1
       goto S2
    ]
    Stop()
]

// this checked 0's and 1's in all cursor memory addresses and
// the x-counter. Now, we must also check the mod 4 shifter
//  i is now =2
//******************************************************************************
and let ClearNBlock() be
[
      {ODataM} = #100 
      ClkStart()
      ClkIAR()

      {ODataM} = #000 ;      // blocks counting 
      ClkStart()
]