//**************************************************************************************
//*** UTVFC6a.TST
//*** Rev. H                                               May 29.1979
//*** Rev. F                                               February 13,1979
//*** V. Vysin                                             
//**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}
//{OData0: Odata.00, Odata.01, Odata.02, Odata.03}
//{OData1: Odata.04, Odata.05, Odata.06, Odata.07}
//{OData2: Odata.08, Odata.09, Odata.10, Odata.11}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{T0: T0D0, T0D1, T0D2, T0D3}
//{T1: T1D0, T1D1, T1D2, T1D3}
//{T2: T2D0, T2D1, T2D2, T2D3}
//{T3: T3D0, T3D1, T3D2, T3D3}
//{Buf0: Buf0B0, Buf0B1, Buf0B2, Buf0B3}
//{Buf1: Buf1B0, Buf1B1, Buf1B2, Buf1B3}
//{Buf2: Buf2B0, Buf2B1, Buf2B2, Buf2B3}
//{Buf3: Buf3B0, Buf3B1, Buf3B2, Buf3B3}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}

// to test the Cursor Memory and associated hardware
let Test62() be
[
   Start()

   // We shall now test the T0 through T3 inputs of TSR
   for i =0 to 1 do
   [
      OddLine()          // to write into even buffer
      {ODataM} = #000;  // to block incrementing in both
      ClkStart()
      NClk(1)
      ClkIAR()

      {OData0} = 5 + 5*i
      {OData1} = 5 + 5*i
      {OData2} = 5 + 5*i
      {OData3} = 5 + 5*i
      EClock()
      WriteAll()
      Switch()      // loads SCR,also loads CR & DR;flipsEvenLine
      NClko(#140)// EvenField=0,PreVS=0,both BlackBgds=1

      {ODataM}= #200
      ClkStart()
      NClk(1)
      {Iaddr.6}= 0
      {Iaddr.7}= 0
      NClk(2)         // to get data to T0,T1
      Compare("T0 register",{T0},5+5*i,"faulty ",100,i)  
      Compare("T1 register",{T1},5+5*i,"faulty ",101,i)
      Compare("T2 register",{T2},5+5*i,"faulty ",102,i)
      Compare("T3 register",{T3},5+5*i,"faulty ",103,i)

      PrepareTSR()
      for m=0 to 23 do
      [
         EClock()
      ]
      for k =0 to 15 do
      [
         let f=16*i+k 
         Compare("Idata.16",{Idata.16},(k+i)rem 2,"Sacrebleu,c'est tres..tres..ehm,wrong",62,f)
         EClock()
      ]
      EndTSR()
      ]

     Stop()
]
and SetCAddr(arg) be
[
	for caa=0 to 3 do
	[
		let cab=arg & 1
		{SRIn'}=cab
		SRClock()
		arg=arg rshift 1
     ]
]

//After this,the rest of the TSR must feel well and so must we.That will be $50.