//**************************************************************************************
//*** UTVFC6.TST
//*** Rev.H                                                 May 29.1979
//*** Rev. F                                                February 8,1979
//*** Rev.B										August 4.1978      
//*** V. Vysin                                             //**************************************************************************************

//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//{ODataM: Odata.00, Odata.01, Odata.02, Odata.03, Odata.04, Odata.05, Odata.06, Odata.07}
//{ODataL:  Odata.08, Odata.09, Odata.10, Odata.11, Odata.12, Odata.13, Odata.14, Odata.15}

//{OData0: Odata.00, Odata.01, Odata.02, Odata.03}
//{OData1: Odata.04, Odata.05, Odata.06, Odata.07}
//{OData2: Odata.08, Odata.09, Odata.10, Odata.11}
//{OData3: Odata.12, Odata.13, Odata.14, Odata.15}
//{T0: T0D0, T0D1, T0D2, T0D3}
//{T1: T1D0, T1D1, T1D2, T1D3}
//{T2: T2D0, T2D1, T2D2, T2D3}
//{T3: T3D0, T3D1, T3D2, T3D3}
//{Buf0: Buf0B0, Buf0B1, Buf0B2, Buf0B3}
//{Buf1: Buf1B0, Buf1B1, Buf1B2, Buf1B3}
//{Buf2: Buf2B0, Buf2B1, Buf2B2, Buf2B3}
//{Buf3: Buf3B0, Buf3B1, Buf3B2, Buf3B3}
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}

// to test the Diagnostic Register

let Test61() be
[
   Start()
   {CTask}=#0 
   SetCAddr(#17) ;   //allimportant;mustrestore MyTask &ICompar
   Compare("MyTask",{MyTask},1,"no chance ",1)
   for a=0 to #77 do
   [
      ClearNBlock()
      OddLine()
      XeroData()
      WriteAll()
   ]
   for a=0 to #77 do
   [
      ClearNBlock()
      EvenLine()
      XeroData()
      WriteAll()
   ]
    // to clear the data buffer again

   ClearNBlock()
   OddLine()                    // to write the even buffer
   
      XeroData()
   WriteBuf(0)

   for i=0 to 3 do
   [
      EvenLine()           // to read the Even buffer
      {ODataM}=#200
      EClock()
      ClkStart()
      NClk(3)        //loads AAR,next loads T2,T3,next loads T0,T1
      Switch()              // loads SCR,also loads CR & DR
      NClko(#150)// EvenField=0,PreVS=1,both BlackBgds=1
      MLpulse()            // should make VS=1
      NClk(1)              // part of ML pulse
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      ClkCR()      // will load DR
      NClk(1)          // sets SendControl 
      Compare("SendControl",{SendControl},1,"went bad ",1,i )
      NClk(2)          //loads all 2+2 T regs
      Compare("T0 register",{T0},4*i +1,"faulty ",2,i)  //VS=1
      Compare("T1 register",{T1},4*i +1,"faulty ",3,i)
      Compare("T2 register",{T2},4*i +1,"faulty ",4,i)
      Compare("T3 register",{T3},4*i +1,"faulty ",5,i)
      SetControlPhase()
      {ODataM} = #200 ;        //  this replaces HS subroutine
      ClkStart()
      NClk(1)
      {OData3} = #4
      WriteHorCont()
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)               // HS is up now
      {OData3} =0
      WriteHorCont()

      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)         // loads T2,T3 and terminates HS,exNibClk=1
      Compare("T2 register",{T2},4*i +3,"faulty ",6,i  )  // VS=1,HS=1
      Compare("T3 register",{T3},4*i +3,"faulty ",7,i  )
      Compare("T0 register",{T0},4*i +1,"faulty ",8,i  )  //still the old one
      Compare("T1 register",{T1},4*i +1,"faulty ",9,i  )
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)
      Compare("T2 register",{T2},4*i +1,"faulty ",10,i  )//returns to the old one
      Compare("T3 register",{T3},4*i +1,"faulty ",11,i  )
      Compare("T0 register",{T0},4*i +3,"faulty ",12,i  ) // now it gets there 
      Compare("T1 register",{T1},4*i +3,"faulty ",13,i  )
      Switch()
      NClko(#140)// EvenField=0,PreVS=0,both BlackBgds=1
      MLpulse()       
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)       // resets VS;now only ExtraNibClk=1
      //Compare("GOTCHA",{RUN},0,"DR ",100)
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)         // ExtraNibTime=0 & loads T2,T3
      Compare("T2 register",{T2},4*i ,"faulty ",14,i  )
      Compare("T3 register",{T3},4*i ,"faulty ",15,i  )
      Compare("T0 register",{T0},4*i +1,"faulty ",16,i  )  //still the old one
      Compare("T1 register",{T1},4*i +1,"faulty ",17,i  )
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)            // resets SendControl
      Compare("T2 register",{T2},4*i ,"faulty ",18,i  )
      Compare("T3 register",{T3},4*i,"faulty ",19,i  )
      {ODataM} = i + 4*i + 16*i + 64*i  ;  //contents of DiagR      
      NClk(1)
      Compare("T0 register",{T0},4*i,"faulty ",20,i  )  
      Compare("T1 register",{T1},4*i,"faulty ",21,i  )

   ]

//  DR is OK with me
//and the SendControl switching (p.12). 
   Stop()
]

and SetCAddr(arg) be
[
	for caa=0 to 3 do
	[
		let cab=arg & 1
		{SRIn'}=cab
		SRClock()
		arg=arg rshift 1
     ]
]

and let ClearNBlock() be
[
      {ODataM} = #100 
      ClkStart()
      ClkIAR()

      {ODataM} = #000 ;      // blocks counting 
      ClkStart()
]