//**************************************************************************************
//*** UTVFC1.TST ***
//*** Updated for Rev.H May 25.1979
//*** Updated for Rev.F January 24. 1979
//*** Updated for Rev.D November 13.1978
//*** Rev.B June21.1978
//*** V.Vysin
//*** First Test program //**************************************************************************************


//**************************************************************************************
//To include the following definition files in the compilation
get "tester.d"
get "UTVFC.d"

//**************************************************************************************
//Test 11: To test Addr Shift-Reg. on p.1
// & Input Addr. Comparator on p.1
//& CTask compare,OMeF and IMeF frip-frop on p.3
//{CTask: CTask.0, CTask.1, CTask.2, CTask.3}
//{IAddr: Iaddr.0, Iaddr.1, Iaddr.2, Iaddr.3, Iaddr.4, Iaddr.5, Iaddr.6, Iaddr.7}

let Test11() be
[
Start()
//SubTest11.1 to clear the Addr Shift-Reg.
for i=0 to 3 do
[
{SRIn’}=0
SRClock()
]
Compare("SROut’", {SROut’}, 0, "UTVFC Address register failed to clear", 1)
// SubTest 11.2 to check the input address Comparator (p1),CTask Compare and OMeF and IMeF //frip-frops (p.3) with travelling block of ones
//pat1 table represents the inverse of the pattern:1000;1100;1110;1111 which gets shifted into CA
//iaddrval1 table represents IAddr bus with the inverse pattern
// and left shift 4-bit to match Caddr
let pat1=table [ #7; #3; #1; #0 ]
let iaddrval1=table [ #160; #060; #020; #000 ]
let k=0
for i=0 to 3 do
[
Compare("SROut",{SROut’},0," v35 outa shape",2,i)
{SRIn’}=1
SRClock()
for j = 0 to 15 do
[
{CTask}=j
test j eq (pat1!i) //compares if CTask compl/Caddr
ifso
[
let k=100*i+j
Compare("MyTask",{MyTask}, 1, "Compare circuit fails",3,k)
{IAddr}=iaddrval1!i ; // ICompare =1
EClock()
Compare("IMeF",{IMeF’}, 1, "failed to reset",4,k)
SetIMeF()
Compare("IMeF",{IMeF’}, 0, "failed to set",5,k)
{IValid’}=1
InputSequ()
Compare("OMeF",{OMeF}, 0, "failed to reset",6,k)
SetOMeF()
Compare("OMeF",{OMeF}, 1, "failed to set",7,k)
ResetOMeF()
]
ifnot
[
let k=100*i+j
Compare("MyTask",{MyTask}, 0, "Compare circuit is stuck at one",8,k)
EClock()
Compare("IMeF",{IMeF’}, 1, "should have been reset",9,k)
Compare("OMeF",{OMeF}, 0, "should have been reset",10,k)
]
]
]
// SubTest 11.3 to check the input address Comparator (p1),CTask Compare and OMeF (p.2) and IMeF (p.3) //frip-frops with travelling block of xeros
//pat2 table represents the inverse of the pattern:0111;0011;0001;0000 which gets shifted into CA
//iaddrval1 table represents IAddr bus with the inverse pattern
// and left shift 4-bit to match Caddr
let pat2=table [ #10; #14; #16; #17 ]
let iaddrval2=table [ #200; #300; #340; #360 ]
let k=0
for i=0 to 3 do
[
Compare("SROut’",{SROut’},1," v35 outa shape",11)
{SRIn’}=0
SRClock()
for j = 0 to 15 do
[
{CTask}=j
test j eq (pat2!i) //compares if CTask compl/Caddr
ifso
[
let k=100*i+j
Compare("MyTask",{MyTask}, 1, "Compare circuit fails",12,k)
{IAddr}=iaddrval2!i ;//ICompare =1
EClock()
Compare("IMeF",{IMeF’}, 1, "failed to reset",13,k)
SetIMeF()
Compare("IMeF",{IMeF’}, 0, "failed to set",14,k)
{IValid’}=1
InputSequ()
Compare("OMeF",{OMeF}, 0, "failed to reset",15,k)
SetOMeF()
Compare("OMeF",{OMeF}, 1, "failed to set",16,k)
ResetOMeF()
]
ifnot
[
let k=100*i+j
Compare("MyTask",{MyTask}, 0, "Compare circuit is stuck at one",17,k)
EClock()
Compare("IMeF",{IMeF’}, 1, "should have been reset",18,k)
Compare("OMeF",{OMeF}, 0, "should have been reset",19,k)
]
]
]


//to set CAddr =1,1,1,1. for Test 2
for i=0 to 3 do
[
{SRIn’}=1
SRClock()
]
{IAddr}=#0; //it is #17 from the previous test
{CTask}=#0; //it is #17 from the previous test

Compare("MyTask",{MyTask},1,"Compare went berserk",20) //just to verify
Compare("SROut’",{SROut’},1,"should be one now",21)
Stop()
]

//after this test : ICompare=1
// ICompr =1
// CAddr=1,1,1,1

//Hereby,the UTVFC Address Register (p.1) ,Input Address Comparator, Current Task
// Comparator(p.3) and OMeF,IMef flip flops (p.1) are declared functional and in fine shape.

//*************************************************************************************

//Test 12: To verify clocks on p.5 (Except cursor related clocks )

//{Clocks: ClkCR’, ClkStart’, ClkIAR’, WriteHorCont’, WriteOddBuf’, WriteEvenBuf’}

and Test12() be
[
Start()
{IAddr}=0 ; //Oaddr 4’, 5’, 6’, 7’ =1111 ... ClkCR’
InputSequ()
{OValid’} =0
Compare("Clocks-",{Clocks},#77,"something stuck at 1 in decode or OARs",1 )
EClock() //OMeF sets
{EdgeClockFeed’} =0
Compare("Clocks",{Clocks},#37,"ClkCR’ decode or OAR2 fails",2 )
{EdgeClockFeed’} =1
ResetOMeF()
{IAddr}=1 ; //Oaddr 4’, 5’, 6’, 7’ =1110 ... ClkStart
InputSequ()
{OValid’} =0
Compare("Clocks-",{Clocks},#77,"something stuck at 1 in decode or OARs",3 )
EClock() //OMeF sets
{EdgeClockFeed’} =0
Compare("Clocks",{Clocks},#57,"ClkStart’ decode or OAR2 fails",4)
{EdgeClockFeed’} =1
ResetOMeF()

{IAddr}=2 ; //Oaddr 4’, 5’, 6’, 7’ =1101 ... WriteHorCont’
InputSequ()
{OValid’} =0
Compare("Clocks-",{Clocks},#77,"something stuck at 1 in decode or OARs",5 )
EClock() //OMeF sets
{RamClockFeed’} =0
Compare("Clocks",{Clocks},#73,"WriteHorCont’ decode or OAR2 fails",6 )
{RamClockFeed’} =1
ResetOMeF()

{IAddr}=3 ; //Oaddr 4’, 5’, 6’, 7’ =1100 ... ClkIAR’
InputSequ()
{OValid’} =0
Compare("Clocks-",{Clocks},#77,"something stuck at 1 in decode or OARs",7 )
EClock() //OMeF sets
{EdgeClockFeed’} =0
Compare("Clocks",{Clocks},#67,"ClkIAR’ decode or OAR2 fails",8 )
{EdgeClockFeed’} =1
ResetOMeF()


{IAddr}=8 ; //Oaddr 4’, 5’, 6’, 7’ =0111 ... Write Even/Odd Buf’/LdIAR’
InputSequ()
{OValid’} =0
Compare("Clocks-",{Clocks},#77,"something stuck at 1 in decode or OARs",9 )
EClock() //OMeF sets
{RamClockFeed’} =0

let e ={EvenLine}
test e eq 1
ifso
[
Compare("Clocks",{Clocks},#75,"Write OddBuf’ decode or OAR2 fails",10 )
]
ifnot
[
Compare("Clocks",{Clocks},#76,"WriteEvenBuf’ decode or OAR2 fails",11 )
]
{RamClockFeed’} =1
{EdgeClockFeed’} =0
Compare("Clocks",{Clocks},#67,"u96c kaput",12 )
{EdgeClockFeed’} =1
ResetOMeF()
Stop()
]

//We now can expect the clock signals to tick well

//**************************************************************************************