//**************************************************************************************
//UTVFC.d
//Definitions for UTVFC.tst
//Common set of external and structure declarations.
//Updated for Rev.H May31,1979
//By V.Vysin August18,1978
//**************************************************************************************

//**************************************************************************************
//Define local, external, and OS routine names
external
[
//UTVFC1.tst
Test11//To test: Address SR,AddrCompare,OMeF,IMeF
Test12//To test: Clocks

//UTVFC1a.tst
Test13//To test: ODR, SAR, Input shifter

//UTVFC2.tst
Test21//To test: IAR, AAR registers, and TSR(partly)
Test22//To test: ControlPhase,BlankTerm.ffs,AAR,IAR counting

//UTVFC2a.tst
Test23//To test: Wake-up logic /Set CAddr subrutine

//UTVFC3.tst
Test31//To test: SetCPhase in HEventRAM
Test32//To test: HS ,Switch and ML bit in HEventRAM
Test33 // To test: EvenLine ff

//UTVFC3a.tst
Test34 //To test: VS ff
Test35 //To test: SendControl logic

//UTVFC4.tst
Test41//To test: Even data buffer, particularly the Buf0 chip
//UTVFC4a.tst
Test42//To test: Even data buffer, particularly the Buf1 chip
//UTVFC4b.tst
Test43//To test: Even data buffer, particularly the Buf2 chip
//UTVFC4c.tst
Test44 //To test: Even data buffer, particularly the Buf3 chip

//UTVFC5.tst
Test51//To test: Odd data buffer, particularly the Buf0 chip
//UTVFC5a.tst
Test52//To test: Odd data buffer, particularly the Buf1 chip
//UTVFC5b.tst
Test53//To test: Odd data buffer, particularly the Buf2 chip
//UTVFC5c.tst
Test54//To test: Odd data buffer, particularly the Buf3 chip

//UTVFC6.tst
Test61//To test: DR&SendControl
//UTVFC6a.tst
Test62//To test: rest of the TSR
//UTVFC6b.tst
Test63// To test:Cursor Memories & associated logic
//UTVFC6c.tst
Test64// To test:Cursor Memories & associated logic


//Subroutines used by various TESTs
Start//Sets up title display, initial conditions, & begins calculation of Run time
Stop//Stops calculation of Run time
Restart//Restarts calculation of Run time
TRun//Controls sequencing of Tests
RClock//Ram Clock
EClock//Edge Clock
Clocks//Ram Clock followed by Edge Clock
InputSequ
SRClock//SR Clock
Reset
ClkCR
ClkStart
ClkIAR
ClkCur
CurWri
WriteHorCont
EvenLine
OddLine
Switch
HSpulse
MLpulse
SetVS
ResetVS
PrepareTSR
EndTSR
SetIMeF
SetOMeF
ResetIMeF
ResetOMeF
SetControlPhase
Compare//Comparison routine
SpaceDisplay//Moves display lines up amount specified
Breakpoint//Breakpoint halt
Delay//Provides variable delay (for display in continuous)
WriteAll
XeroData

//Macros
SetCaddr
NClko
SetOaddr //sets a given Oaddress
NClk //Nibble Clock
LoadAAR
LoadIAR
WriteBuf

//OS functions
DisplayString
Ws
Quit
Endofs
Gets
keys
FORMATN
DefaultArgs
Noop

//Variables
ParErr
looping
cont
testno
testtime
truntime
starttime
runtime
]

//**************************************************************************************
//Define template
structure w:
[
b0: bit
b1: bit
b2: bit
b3: bit
b4: bit
b5: bit
b6: bit
b7: bit
b8: bit
b9: bit
b10: bit
b11: bit
b12: bit
b13: bit
b14: bit
b15: bit
]

//**************************************************************************************