//**************************************************************************************
//RDC.d
//Definitions for RDC.tst
//Common set of external and structure declarations.
//By J. F. CameronJune 27, 1978
//Last modified by J. F. CameronJune 13, 1980
//**************************************************************************************

//**************************************************************************************
//Define local, external, and OS routine names
external
[
//RDC1.tstProcessor Interface Tests
Test11//To test:Caddr Register
Test12//To test:ICompare; IMeF
Test13//To test:OMeF
Test14//To test:Idata (IDWord)
Test15//To test:Reset; OFault; Run; Abort (set by OFaultF & Write Fault)

//RDC2.tstDevice Simulator & Interface Tests
Test21//To test:Dr/Hd Select; Drive Interface; Idata (TestGroup)
Test22//To test:Idata(Status); Test Register; Sector Mark; DevSelOK; Dev Clock
Test23//To test:Timing Gen; ByteClk
Test24//To test:Sector00
Test25//To test:ReadGate
Test26//To test:WriteGate
Test27//To test:FaultClear’
Test28//To test:MyTask; IOAttn

//RDC3.tstSequence Address Generator Tests
Test31//To test:Sequence Address Generation
Test32//To test:Seek Control

//RDC4.tstData Buffer Tests
Test41//To test:DevBufAdr Register
Test42//To test:MemBufAdr Register
Test43//To test:Buffer Data Path to and from Processor

//RDC5.tstSerializer/Deserializer Tests
Test51//To test:Dev ← Buffer Data; Shifter; Buffer ← Dev Data
Test52//To test:Sync Detector
Test53//To test:DevWrtData’
Test54//To test:Compare Logic

//RDC6.tstDevice Format Sequencer Control Tests
Test61//To test:Address Selection
Test62//To test:Branch Control

//RDC7.tstBuffer Control Sequencer Control Tests
Test71//To test:Address Selection
Test72//To test:Counter Branch
Test73//To test:Xfer Branch

//RDC8.tstError Detection & Control Tests
Test81//To test:CRC Generation
Test82//To test:ECC Generation
Test83//To test:ECC Check
Test84//To test:Service Late
Test85//To test:Control; Compare(verify); Buf Par Check

//RDC9.tstWake Generator Tests
Test91//To test:RDC Generated Wake & Reset
Test92//To test:Data Wake Count

//Subroutines used by various TESTs
Start//Sets up title display, initial conditions, & begins calculation of Run time
Stop//Stops calculation of Run time
TRun//Controls sequencing of Tests
RClock//Ram Clock
EClock//Edge Clock
Clocks//Ram Clock followed by Edge Clock
SRClock//SR Clock
EnableDevClk//Enables DevClk
Compare//Comparison routine
SpaceDisplay//Moves display lines up amount specified
Breakpoint//Breakpoint halt
Delay//Provides variable delay (for display in continuous)

//Macros
OData
IData
SetCaddr

//OS functions
DisplayString
Ws
Quit
Endofs
Gets
keys
FORMATN
DefaultArgs
Noop

//Variables
ParErr
looping
cont
testno
idt
pass
again
failures
]

//**************************************************************************************
//Define template
structure w:
[
b0: bit
b1: bit
b2: bit
b3: bit
b4: bit
b5: bit
b6: bit
b7: bit
b8: bit
b9: bit
b10: bit
b11: bit
b12: bit
b13: bit
b14: bit
b15: bit
]

//**************************************************************************************
//to define constants
manifest
[
Caddr = 12b

//Output Register Functions
GeneralReset = 00b
DrHdRegLd = 01b
ErrReset = 02b
DevOpRegLd = 03b
BufDataLd = 04b
TestRegLd = 05b
MemBufAdrLd = 06b
PrimeIData = 07b

//Input Register Functions
IDWord = 00b
Status = 01b
Test = 12b
Buf = 17b
]