%

*** *** *** *** ***         <D0Diag>Edalu.mc  Rev 1.1  May 3, 1980        *** *** *** *** ***   

****************************************************************************************
*** EDALU.mc : Central-data-paths-exerciser microcode  
***   Purpose  : This test exercises some basic functions of the ALU module.
***   Hardware Configuration  : Standard 4 CPU boards.
***   Written by  : (unknown)
***   Modified by : C. Thacker,  June 16, 1979
***   Modified by : M. Thomson & J. Kellman,  Jan. 8, 1979
         Standardize title page and code format.
***   Modified by : C. Thacker,  May 3, 1980
	Standardized assembly procedure with alu.cm, changed for new D0lang
****************************************************************************************   



****************************************************************************************
* SubTest Description:
*   Subtests are indicated in the flow charts and .mc file by:
*     1) Mcount (in octal)
*     2) Mpanel (in decimal)

****************************************************************************************
* Subroutine Description:
*   compare0:  Compares contents of s0 (R file) with T
*   poptst:    Checks the contents of the stack after it has been loaded by push operations
*   TchkR:     Takes pattern in T, break points if discrepency is found 
*   TfillR:    Write pattern in T from Rmax through Rmin in R file

****************************************************************************************
* Breakpoints:
*   AchkRer:   Value in R did not match R address. 
*   badnotify: Task failed to switch.
*   fail:      Value in s0 (R file) did not match value in T.
*   TchkRer0:  Value in s1 (R file) did not match value in T.
*   TchkRer1:  Value in s0 (R file) did not match value in T.
*   TchkRer2:  Value in stack did not match stack address.
*   TfillRer:  Value in s1 (R file) did not match value in T.
*   Passed-EDALU-Test:  the system passed thru all the passes of EDALU.

****************************************************************************************
* Breakpoint Logic Analyzer Sync Points:
*   AchkRer
*   badnotify
*   fail
*   TchkRer0
*   TchkRer1
*   TchkRer2
*   TfillRer
*   Passed-EDALU-Test

****************************************************************************************

%

****************************************************************************************
* INITIALIZATION:

TITLE[Central-data-paths-exerciser];

**********  Set constants:  ***********

***  Code to page allocation:  ***

***  Page  ***		***  principal entry points  ***

SET[Rpage, 1];		* stktst, flone, flzero, TfillR, TchkR, AfillR, AchkR
SET[pushpage, 2];	* push1, pushm1, push2, pushm2, push3, pushm3
SET[popxpage, 3];	* poptst extension: pop3, popm3
SET[poppage, 4];	* poptst: pop1, popm1, pop2e, pop2o, popm2e, popm2o
SET[alupage, 5];	* go, contst, acontst, alutst

**********  Macro definitions:  *******

M@[ones, (ZERO)-1];

* compares s0 with T, break point results if the two are not equal
M@[compare,
  IFG[10,FVAL[PGE@],
    SELECT[FVAL[PGE@], call[compare0], call[compare1], call[compare2],
      call[compare3], call[compare4], call[compare5], call[compare6],
      call[compare7]],
    SELECT[SUB[FVAL[PGE@], 10], call[compare10], call[compare11],
      call[compare12], call[compare13], call[compare14], call[compare15],
      call[compare16], call[compare17]]]];

**********  Macro constants:  *********

MC[Rmin, 20];  		* First R location tested
MC[Rmax, 317]; 		* Last R location tested

MC[faultTrapLoc, 0];	* special control store locations used by hardware
MC[bootTrapLoc, 1];

**********  R-registers:  *************

RV[s0, 0];		* R store temporaries
RV[s1, 1];
RV[rt, 2];		* stack test iterations count
RV[oldapc, 3];		* holds return address during poptst
RV[revision,4,1];	* revision number is 1 for this program
RV[Mcount,5];		* octal equivalent of maintenance panel display
RV[Run-time,6,11];	* run time for this test is 9 seconds
RV[PassCount,7,0];	* pass count for this program
RV[MaxPass,10,1000];	* maximum number of passes for this run

****************************************************************************************
*** PRELIMINARY routine:

SET[sTestBase,lshift[alupage,10]];
MC[sTestTask,add[sTestBase,150000]];
MC[sTestBC,sTestBase];

ON PAGE[alupage];

start:
go:	clearMpanel; Mcount _ ZERO;	* initialize Mpanel to 0000, Mcount to 0000

	s0 _ sTestBC;
	APCtask&APC _ s0;
	return;				* generate task switch

badnotify: breakpoint, goto[go];	* should never reach here

	* set tasks 1-15 to breakpoint if awakened

T0:	s0 _ sTestTask, at[sTestBC!]; 	* task 15
	s0 _ (s0) or (20C);
bwnotify: apc&apctask _ s0;
	return;

	s0 _ (s0) - (10000C), at[add[sTestBase,31]]; *notify returns to here
	LU _ ldf[s0,0,4];
	dblgoto[bwnotify,TtoR,alu#0];

bwnot:	s1 _ sTestBC,call[xret], at[add[sTestBase,20]];
badwake: usectask;
	T _ apc&apctask;
	breakpoint, goto[go];
	return;

xret:	s1 _ (s1) or (31C);
	apc&apctask _ s1;
	return;

	* guaranteed to be in task 0 now

****************************************************************************************
*** MAIN routine:

	* try the T pass around path

TtoR:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0001, Mcount to 0001

	s0 _ T _ 0C;
	T _ 377C;
	s0 _ T;
	compare;

	* try the R pass around path

RtoT:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0002, Mcount to 0002

	s0 _ T _ 0C;
	s0 _ 377C;
	T _ s0;
	compare;

	* test constants from micro instruction

contst: incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0003, Mcount to 0003

	s0 _ (ZERO);      T _ 0C;	compare;
	s0 _ (ZERO) + 1;  T _ 1C;	compare;
	s0 _ (s0) + (T);  T _ 2C;	compare;
	s0 _ (s0) + (T);  T _ 4C;	compare;
	s0 _ (s0) + (T);  T _ 10C;	compare;
	s0 _ (s0) + (T);  T _ 20C;	compare;
	s0 _ (s0) + (T);  T _ 40C;	compare;
	s0 _ (s0) + (T);  T _ 100C;	compare;
	s0 _ (s0) + (T);  T _ 200C;	compare;
	s0 _ (s0) + (T);  T _ 400C;	compare;
	s0 _ (s0) + (T);  T _ 1000C;	compare;
	s0 _ (s0) + (T);  T _ 2000C;	compare;
	s0 _ (s0) + (T);  T _ 4000C;	compare;
	s0 _ (s0) + (T);  T _ 10000C;	compare;
	s0 _ (s0) + (T);  T _ 20000C;	compare;
	s0 _ (s0) + (T);  T _ 40000C;	compare;
	s0 _ (s0) + (T);  T _ 100000C;	compare;

	* test the basic ALU operations

alutst: incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0004, Mcount to 0004

	s0 _ ZERO;		* test cycler/masker function ZERO
	T _ 0C;
	compare;

	s0 _ 0C;		* test (ZERO) - 1
	s1 _ T _ ones;		* set s1 to all ones for subsequent tests
	T _ (ZERO) + (T) + 1;
	compare;

alu0:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0005, Mcount to 0005

	T _ ones;		* 1 from T
	s0 _ T;
	compare;

	T _ 0C;			* 0 from T
	s0 _ T;
	compare;

alu1:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0006, Mcount to 0006

	s0 _ 0C;
	T _ s0;			* 0 from R
	compare;

	s0 _ ones;		* 1 from R
	T _ s0;
	compare;

alu2:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0007, Mcount to 0007

	T _ 0C;		T _ (ZERO) and (T);	* 0 and 0
	s0 _ 0C;	compare;

	T _ ones;	T _ (ZERO) and (T);	* 0 and 1
	s0 _ 0C;	compare;

	T _ 0C;		T _  (s1)  and (T);	* 1 and 0
	s0 _ 0C;	compare;

	T _ ones;	T _  (s1)  and (T);	* 1 and 1
	s0 _ ones;	compare;

alu3	:incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0008, Mcount to 0010

	T _ 0C;		T _ (ZERO) or (T);	* 0 or 0
	s0 _ 0C;	compare;

	T _ ones;	T _ (ZERO) or (T);	* 0 or 1
	s0 _ ones;	compare;

	T _ 0C;		T _  (s1)  or (T);	* 1 or 0
	s0 _ ones;	compare;

	T _ ones;	T _  (s1)  or (T);	* 1 or 1
	s0 _ ones;	compare;

alu4:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0009, Mcount to 0011

	T _ 0C;		T _ (ZERO) xor (T);	* 0 xor 0
	s0 _ 0C;	compare;

	T _ ones;	T _ (ZERO) xor (T);	* 0 xor 1
	s0 _ ones;	compare;

	T _ 0C;		T _  (s1)  xor (T);	* 1 xor 0
	s0 _ ones;	compare;

	T _ ones;	T _  (s1)  xor (T);	* 1 xor 1
	s0 _ 0C;	compare;

alu5:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0010, Mcount to 0012

	T _ 0C;		T _ (ZERO) andnot (T);	* 0 andnot 0
	s0 _ 0C;	compare;

	T _ ones;	T _ (ZERO) andnot (T);	* 0 andnot 1
	s0 _ 0C;	compare;

	T _ 0C;		T _  (s1)  andnot (T);	* 1 andnot 0
	s0 _ ones;	compare;

	T _ ones;	T _  (s1)  andnot (T);	* 1 andnot 1
	s0 _ 0C;	compare;

alu6:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0011, Mcount to 0013

	T _ 0C;		T _ (ZERO) ornot (T);	* 0 ornot 0
	s0 _ ones;	compare;

	T _ ones;	T _ (ZERO) ornot (T);	* 0 ornot 1
	s0 _ 0C;	compare;

	T _ 0C;		T _  (s1)  ornot (T);	* 1 ornot 0
	s0 _ ones;	compare;

	T _ ones;	T _  (s1)  ornot (T);	* 1 ornot 1
	s0 _ ones;	compare;

alu7:	incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0012, Mcount to 0014

	T _ 0C;		T _ (ZERO) xnor (T);	* 0 xnor 0
	s0 _ ones;	compare;

	T _ ones;	T _ (ZERO) xnor (T);	* 0 xnor 1
	s0 _ 0C;	compare;

	T _ 0C;		T _  (s1)  xnor (T);	* 1 xnor 0
	s0 _ 0C;	compare;

	T _ ones;	T _  (s1)  xnor (T);	* 1 xnor 1
	s0 _ ones;	compare;

	LOAD PAGE[Rpage];
	gotop[stktst];

****************************************************************************************

ON PAGE[Rpage];

	* try the stack pointer

stktst: incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0013, Mcount to 0015

	T _ s0 _ Rmax;
	stkp _ s0;
	T _ stkp;
	s1 _ 377C;
	T _ (s1) and (T);
	T _ (s1) xor (T);		* stkp comes back complemented
	compare;

	* exercise the entire R store access through the stkp

flone:	T _ 0C;		call[TfillR];	* increment Mpanel to 0014, Mcount to 0016
	T _ 0C;		call[TchkR];

	T _ 1C;		call[TfillR];	* increment Mpanel to 0015, Mcount to 0017
	T _ 1C;		call[TchkR];

	T _ 2C;		call[TfillR];	* increment Mpanel to 0016, Mcount to 0020
	T _ 2C;		call[TchkR];

	T _ 4C;		call[TfillR];	* increment Mpanel to 0017, Mcount to 0021
	T _ 4C;		call[TchkR];

	T _ 10C;	call[TfillR];	* increment Mpanel to 0018, Mcount to 0022
	T _ 10C;	call[TchkR];

	T _ 20C;	call[TfillR];	* increment Mpanel to 0019, Mcount to 0023
	T _ 20C;	call[TchkR];

	T _ 40C;	call[TfillR];	* increment Mpanel to 0020, Mcount to 0024
	T _ 40C;	call[TchkR];

	T _ 100C;	call[TfillR];	* increment Mpanel to 0021, Mcount to 0025
	T _ 100C;	call[TchkR];

	T _ 200C;	call[TfillR];	* increment Mpanel to 0022, Mcount to 0026
	T _ 200C;	call[TchkR];

	T _ 400C;	call[TfillR];	* increment Mpanel to 0023, Mcount to 0027
	T _ 400C;	call[TchkR];

	T _ 1000C;	call[TfillR];	* increment Mpanel to 0024, Mcount to 0030
	T _ 1000C;	call[TchkR];

	T _ 2000C;	call[TfillR];	* increment Mpanel to 0025, Mcount to 0031
	T _ 2000C;	call[TchkR];

	T _ 4000C;	call[TfillR];	* increment Mpanel to 0026, Mcount to 0032
	T _ 4000C;	call[TchkR];

	T _ 10000C;	call[TfillR];	* increment Mpanel to 0027, Mcount to 0033
	T _ 10000C;	call[TchkR];

	T _ 20000C;	call[TfillR];	* increment Mpanel to 0028, Mcount to 0034
	T _ 20000C;	call[TchkR];

	T _ 40000C;	call[TfillR];	* increment Mpanel to 0029, Mcount to 0035
	T _ 40000C;	call[TchkR];

	T _ 100000C;	call[TfillR];	* increment Mpanel to 0030, Mcount to 0036
	T _ 100000C;	call[TchkR];

flzero: T _ 0C;		T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0031, Mcount to 0037
	T _ 0C;		T _ (ZERO) ornot (T);  call[TchkR];

	T _ 1C;		T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0032, Mcount to 0040
	T _ 1C;		T _ (ZERO) ornot (T);  call[TchkR];

	T _ 2C;		T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0033, Mcount to 0041
	T _ 2C;		T _ (ZERO) ornot (T);  call[TchkR];

	T _ 4C;		T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0034, Mcount to 0042
	T _ 4C;		T _ (ZERO) ornot (T);  call[TchkR];

	T _ 10C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0035, Mcount to 0043
	T _ 10C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 20C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0036, Mcount to 0044
	T _ 20C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 40C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0037, Mcount to 0045
	T _ 40C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 100C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0038, Mcount to 0046
	T _ 100C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 200C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0039, Mcount to 0047
	T _ 200C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 400C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0040, Mcount to 0050
	T _ 400C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 1000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0041, Mcount to 0051
	T _ 1000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 2000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0042, Mcount to 0052
	T _ 2000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 4000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0043, Mcount to 0053
	T _ 4000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 10000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0044, Mcount to 0054
	T _ 10000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 20000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0045, Mcount to 0055
	T _ 20000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 40000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0046, Mcount to 0056
	T _ 40000C;	T _ (ZERO) ornot (T);  call[TchkR];

	T _ 100000C;	T _ (ZERO) ornot (T);  call[TfillR]; * incr. Mpanel to 0047, Mcount to 0057
	T _ 100000C;	T _ (ZERO) ornot (T);  call[TchkR];

	* write address in contents all through R

AfillR: incMpanel, Mcount _ (Mcount) + 1; * increment Mpanel to 0048, Mcount to 0060

	s0 _ T _ Rmax;
AfillRl: stkp _ s0;
	stack _ T;
	s0 _ T _ (s0)-1;
	LU _ (s0) - (Rmin);
	goto[AfillRl, ALU>=0];

	* check that address is in contents all through R

AchkR:	s0 _ T _ Rmax;
AchkRl:	stkp _ s0;
	LU _ (stack) # T;
	goto[.+2, ALU=0];
AchkRer:  breakpoint;		* contents do not match address
	s0 _ T _ (s0)-1;
	LU _ (s0) - (Rmin);
	goto[AchkRl, ALU>=0];

	LOAD PAGE[pushpage];
	gotop[push1];



**********  start SUBROUTINE: TfillR  **********

	* write pattern in T from Rmax through Rmin in R store, increment Mpanel and Mcount
	* 	s0 holds address
	* 	s1 holds pattern

TfillR: incMpanel, Mcount _ (Mcount) + 1;
	s1 _ T;
	LU _ (s1) # T;
	goto[.+2, ALU=0];
TfillRer: breakpoint, goto[.-3];		* pattern and T disagree
	s0 _ Rmax;
TfillRl: stkp _ s0;
	stack _ T;
	s0 _ (s0) - 1;
	LU _ (s0) - (Rmin);
	goto[TfillRl, ALU>=0];
	T _ s1;
	s0 _ T, return;



**********  start SUBROUTINE: TchkR  **********

	* takes pattern in T, break points if discrepency is found

TchkR:  LU _ (s1) # T;		* special check on pattern
	goto[.+2, ALU=0];
TchkRer0: breakpoint;		* pattern and T disagree
	LU _ (s0) # T;		* TfillR put the pattern in S0 as part of a RETURN (checks
				* that R writes are done properly across TASK switches)
	goto[.+2, ALU=0];
TchkRer1: breakpoint;
	s0 _ Rmax;
TchkRl: stkp _ s0;		* stkp loaded from ALUA, sigh
	LU _ (stack) # T;
	goto[.+2, ALU=0];
TchkRer2: breakpoint;		* pattern does not match R
	s0 _ (s0) -1;
	LU _ (s0) - (Rmin);
	goto[TchkRl, ALU>=0];
	return;

****************************************************************************************

ON PAGE[pushpage];

	* test stack push and pop operations

push1:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0049 and Mcount to 0061

	s0 _ 37C;  stkp _ s0;	* use regs. 20-37 for this test (init. to 37 for increment to 20)
	s1 _ T _ 20C;		* starting data (to be stored in address 20)
	rt _ 17C;		* iterations count for 20 iterations

push1l:	stack&+1 _ T;		* store data in incremented stack (will increment mod. 20)
	s1 _ T _ (s1) + 1;	* increment data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[push1l, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents



pushm1:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0050 and Mcount to 0062

	s0 _ 20C;  stkp _ s0;	* use regs. 37-20 for this test (init. to 20 for decrement to 37)
	s1 _ T _ 37C;		* starting data (to be stored in address 37)
	rt _ 17C;		* iterations count for 20 iterations

pushm1l:	stack&-1 _ T;	* store data in decremented stack (will decrement mod. 20)
	s1 _ T _ (s1) - 1;	* decrement data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[pushm1l, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents



push2:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0051 and Mcount to 0063

	s0 _ 36C;  stkp _ s0;	* use even regs. 20-36 for this test (init. to 36 for increment to 20)
	s1 _ T _ 20C;		* starting data (to be stored in address 20)
	rt _ 7C;		* iterations count for 10 iterations

push2le:	stack&+2 _ T;	* store data in incremented stack (will increment mod. 20)
	s1 _ T _ (s1) + (2C);	* increment data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[push2le, ALU>=0];

	s0 _ 37C;  stkp _ s0;	* use odd regs. 21-37 for this test (init. to 37 for increment to 21)
	s1 _ T _ 21C;		* starting data (to be stored in address 21)
	rt _ 7C;		* iterations count for 10 iterations

push2lo:	stack&+2 _ T;	* store data in incremented stack (will increment mod. 20)
	s1 _ T _ (s1) + (2C);	* increment data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[push2lo, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents



pushm2:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0052 and Mcount to 0064

	s0 _ 20C;  stkp _ s0;	* use even regs. 36-20 for this test (init. to 20 for decrement to 36)
	s1 _ T _ 36C;		* starting data (to be stored in address 36)
	rt _ 7C;		* iterations count for 10 iterations

pushm2le:	stack&-2 _ T;	* store data in decremented stack (will decrement mod. 20)
	s1 _ T _ (s1) - (2C);	* decrement data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[pushm2le, ALU>=0];

	s0 _ 21C;  stkp _ s0;	* use odd regs. 37-21 for this test (init. to 21 for decrement to 37)
	s1 _ T _ 37C;		* starting data (to be stored in address 37)
	rt _ 7C;		* iterations count for 10 iterations

pushm2lo:	stack&-2 _ T;	* store data in decremented stack (will decrement mod. 20)
	s1 _ T _ (s1) - (2C);	* decrement data to be stored
	rt _ (rt) - 1;		* decrement iterations count
	goto[pushm2lo, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents



push3:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0053 and Mcount to 0065

	s0 _ 35C;  stkp _ s0;	* use regs. 20-37 for this test (init. to 35 for increment to 20)
	s1 _ T _ 20C;		* starting data (to be stored in address 20)
	rt _ 17C;		* iterations count for 20 iterations

push3l:	stack&+3 _ T;		* store data in incremented stack (will increment mod. 20)
	s1 _ (s1) + (3C);
	s1 _ (s1) and (17C);
	s1 _ T _ (s1) + (20C);	* data incremented by 3's (mod. 20)

	rt _ (rt) - 1;		* decrement iterations count
	goto[push3l, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents



pushm3:	T _ ones;
	LOAD PAGE[Rpage];
	callp[TfillR];		* initialize area to -1, increment Mpanel to 0054 and Mcount to 0066

	s0 _ 20C;  stkp _ s0;	* use regs. 37-20 for this test (init. to 20 for decrement to 35)
	s1 _ T _ 35C;		* starting data (to be stored in address 35)
	rt _ 17C;		* iterations count for 20 iterations

pushm3l:	stack&-3 _ T;	* store data in decremented stack (will decrement mod. 20)

	s1 _ (s1) - (3C);
	s1 _ (s1) and (17C);
	s1 _ T _ (s1) + (20C);	* data decremented by 3's (mod. 20)

	rt _ (rt) - 1;
	goto[pushm3l, ALU>=0];

	LOAD PAGE[poppage];
	callp[poptst];		* check proper contents


	PassCount _ (PassCount) + 1;	* increment pass count
	T _ MaxPass;
	lu _ (PassCount) - (T);
	goto[.+3,ALU>=0];		* finished all passes?
	LOAD PAGE[alupage];
	gotop[go];

Passed-EDALU-Test: PassCount _ 0C, breakpoint;

	LOAD PAGE[alupage];
	gotop[go];

****************************************************************************************

ON PAGE[poppage];

**********  start SUBROUTINE: poptst  **********

poptst: usectask;
	T _ apc&apctask;	* save the return address
	oldapc _ T;

pop1:   s0 _ 20C;
	stkp _ s0;
	T _ (stack&+1);		* retrieves and then increments
	compare;

	s0 _ 21C;  T _ (stack&+1);  compare;
	s0 _ 22C;  T _ (stack&+1);  compare;
	s0 _ 23C;  T _ (stack&+1);  compare;
	s0 _ 24C;  T _ (stack&+1);  compare;
	s0 _ 25C;  T _ (stack&+1);  compare;
	s0 _ 26C;  T _ (stack&+1);  compare;
	s0 _ 27C;  T _ (stack&+1);  compare;
	s0 _ 30C;  T _ (stack&+1);  compare;
	s0 _ 31C;  T _ (stack&+1);  compare;
	s0 _ 32C;  T _ (stack&+1);  compare;
	s0 _ 33C;  T _ (stack&+1);  compare;
	s0 _ 34C;  T _ (stack&+1);  compare;
	s0 _ 35C;  T _ (stack&+1);  compare;
	s0 _ 36C;  T _ (stack&+1);  compare;
	s0 _ 37C;  T _ (stack&+1);  compare;
	s0 _ 20C;  T _ (stack&+1);  compare;

popm1:  s0 _ 20C;
	stkp _ s0;
	T _ (stack&-1);
	compare;

	s0 _ 37C;  T _ (stack&-1);  compare;
	s0 _ 36C;  T _ (stack&-1);  compare;
	s0 _ 35C;  T _ (stack&-1);  compare;
	s0 _ 34C;  T _ (stack&-1);  compare;
	s0 _ 33C;  T _ (stack&-1);  compare;
	s0 _ 32C;  T _ (stack&-1);  compare;
	s0 _ 31C;  T _ (stack&-1);  compare;
	s0 _ 30C;  T _ (stack&-1);  compare;
	s0 _ 27C;  T _ (stack&-1);  compare;
	s0 _ 26C;  T _ (stack&-1);  compare;
	s0 _ 25C;  T _ (stack&-1);  compare;
	s0 _ 24C;  T _ (stack&-1);  compare;
	s0 _ 23C;  T _ (stack&-1);  compare;
	s0 _ 22C;  T _ (stack&-1);  compare;
	s0 _ 21C;  T _ (stack&-1);  compare;
	s0 _ 20C;  T _ (stack&-1);  compare;

pop2e:  s0 _ 20C;
	stkp _ s0;
	T _ (stack&+2);
	compare;

	s0 _ 22C;  T _ (stack&+2);  compare;
	s0 _ 24C;  T _ (stack&+2);  compare;
	s0 _ 26C;  T _ (stack&+2);  compare;
	s0 _ 30C;  T _ (stack&+2);  compare;
	s0 _ 32C;  T _ (stack&+2);  compare;
	s0 _ 34C;  T _ (stack&+2);  compare;
	s0 _ 36C;  T _ (stack&+2);  compare;
	s0 _ 20C;  T _ (stack&+2);  compare;

pop2o:  s0 _ 21C;
	stkp _ s0;
	T _ (stack&+2);
	compare;

	s0 _ 23C;  T _ (stack&+2);  compare;
	s0 _ 25C;  T _ (stack&+2);  compare;
	s0 _ 27C;  T _ (stack&+2);  compare;
	s0 _ 31C;  T _ (stack&+2);  compare;
	s0 _ 33C;  T _ (stack&+2);  compare;
	s0 _ 35C;  T _ (stack&+2);  compare;
	s0 _ 37C;  T _ (stack&+2);  compare;
	s0 _ 21C;  T _ (stack&+2);  compare;

popm2e: s0 _ 20C;
	stkp _ s0;
	T _ (stack&-2);
	compare;

	s0 _ 36C;  T _ (stack&-2);  compare;
	s0 _ 34C;  T _ (stack&-2);  compare;
	s0 _ 32C;  T _ (stack&-2);  compare;
	s0 _ 30C;  T _ (stack&-2);  compare;
	s0 _ 26C;  T _ (stack&-2);  compare;
	s0 _ 24C;  T _ (stack&-2);  compare;
	s0 _ 22C;  T _ (stack&-2);  compare;
	s0 _ 20C;  T _ (stack&-2);  compare;

popm2o: s0 _ 21C;
	stkp _ s0;
	T _ (stack&-2);
	compare;

	s0 _ 37C;  T _ (stack&-2);  compare;
	s0 _ 35C;  T _ (stack&-2);  compare;
	s0 _ 33C;  T _ (stack&-2);  compare;
	s0 _ 31C;  T _ (stack&-2);  compare;
	s0 _ 27C;  T _ (stack&-2);  compare;
	s0 _ 25C;  T _ (stack&-2);  compare;
	s0 _ 23C;  T _ (stack&-2);  compare;
	s0 _ 21C;  T _ (stack&-2);  compare;

	LOAD PAGE[popxpage];
	gotop[pop3];

****************************************************************************************

ON PAGE[popxpage];

pop3:   s0 _ 20C;
	stkp _ s0;
	T _ (stack&+3);
	compare;

	s0 _ 23C;  T _ (stack&+3);  compare;
	s0 _ 26C;  T _ (stack&+3);  compare;
	s0 _ 31C;  T _ (stack&+3);  compare;
	s0 _ 34C;  T _ (stack&+3);  compare;
	s0 _ 37C;  T _ (stack&+3);  compare;
	s0 _ 22C;  T _ (stack&+3);  compare;
	s0 _ 25C;  T _ (stack&+3);  compare;
	s0 _ 30C;  T _ (stack&+3);  compare;
	s0 _ 33C;  T _ (stack&+3);  compare;
	s0 _ 36C;  T _ (stack&+3);  compare;
	s0 _ 21C;  T _ (stack&+3);  compare;
	s0 _ 24C;  T _ (stack&+3);  compare;
	s0 _ 27C;  T _ (stack&+3);  compare;
	s0 _ 32C;  T _ (stack&+3);  compare;
	s0 _ 35C;  T _ (stack&+3);  compare;
	s0 _ 20C;  T _ (stack&+3);  compare;

popm3:  s0 _ 20C;
	stkp _ s0;
	T _ (stack&-3);
	compare;

	s0 _ 35C;  T _ (stack&-3);  compare;
	s0 _ 32C;  T _ (stack&-3);  compare;
	s0 _ 27C;  T _ (stack&-3);  compare;
	s0 _ 24C;  T _ (stack&-3);  compare;
	s0 _ 21C;  T _ (stack&-3);  compare;
	s0 _ 36C;  T _ (stack&-3);  compare;
	s0 _ 33C;  T _ (stack&-3);  compare;
	s0 _ 30C;  T _ (stack&-3);  compare;
	s0 _ 25C;  T _ (stack&-3);  compare;
	s0 _ 22C;  T _ (stack&-3);  compare;
	s0 _ 37C;  T _ (stack&-3);  compare;
	s0 _ 34C;  T _ (stack&-3);  compare;
	s0 _ 31C;  T _ (stack&-3);  compare;
	s0 _ 26C;  T _ (stack&-3);  compare;
	s0 _ 23C;  T _ (stack&-3);  compare;
	s0 _ 20C;  T _ (stack&-3);  compare;

	apc&apctask _ oldapc;
	return;

************  end SUBROUTINE: poptst  **********

****************************************************************************************

ONPAGE[0];

**********  start SUBROUTINE: compare0  **********

compare0: LU _ (s0) # (T);
	goto[success, ALU=0];
fail:   breakpoint;
success:return;

************  end SUBROUTINE: compare0  **********

***  similarly:  ***

ONPAGE[1];
compare1: LOADPAGE[0];
	gotop[compare0];
ONPAGE[2];
compare2: LOADPAGE[0];
	gotop[compare0];
ONPAGE[3];
compare3: LOADPAGE[0];
	gotop[compare0];
ONPAGE[4];
compare4: LOADPAGE[0];
	gotop[compare0];
ONPAGE[5];
compare5: LOADPAGE[0];
	gotop[compare0];

        end;