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*** *** *** *** *** <D0Diag>Edtnf.mc Rev. 1.1 May 3, 1980 *** *** *** *** ***
****************************************************************************************
*** EDTNF.mc : microcode to test-new-features
*** Purpose : This test checks the automatic NewInst feature, the ByteCode register,
the IntPending flag (bit 12 of the RS232 interface), the H2Bit8 flag,
and the new field descriptors .
*** Hardware Configuration : Standard 4 CPU boards.
*** Written by : (unknown)
*** Modified by : C. Thacker, Dec. 15, 1978
*** Modified by : C. Thacker, Jan. 25, 1979
Built version for early prototypes without ByteCode register.
*** Modified by : C. Thacker, Jan. 27, 1979
Put ByteCode register test back.
*** Modified by : J. Kellman, Jan. 10, 1980
Standardize title page and code format.
*** Modified by : C. Thacker, May 3, 1980
standardized assembly procedure with tnf.cm, fixed for new d0lang.
****************************************************************************************
****************************************************************************************
* Subroutine Description:
* Note: There are fifty-two single instruction subroutines, each consisting
of a single RETURN. These are used as possible targets when testing
the automatic NewInst feature.
* SetRet: because of its location at CS address 2015, this one-instruction subroutine
causes sstkp to get the value of stkp.
****************************************************************************************
* Breakpoints:
* ShouldHaveButDidnt: NewInst should have loaded sstkp but didn’t.
* ShouldntHaveButDid: NewInst shouldn’t have loaded sstkp but did.
* IntPBad1: failed to see IntPending when IntPending bit was set.
* IntPBad: saw IntPending even though IntPending bit was reset.
* Target377: the IntPending condition failed to force the NextInst dispatch to go
to Target0.
* WrongPlace: NextInst dispatch went to the wrong place.
* CIAFailed: target of NextInst dispatch failed to save the proper CIA value.
* APCFailed: NIRET failed to load the proper dispatch addr. into APC.
* H2b8StuckLow: H2Bit8 condition failed to see bit 8 of H2 set.
* H2b8StuckHigh: H2Bit8 condition failed to see bit 8 of H2 reset.
* FixVAbad: the FixVA instr. failed to convert 100200 octal into 40100 octal.
* Form2Bad: the field descriptor to form a 2 from -1 failed to do so.
* Form4Bad: the field descriptor to form a 4 from -1 failed to do so.
* Form5Bad: the field descriptor to form a 5 from -1 failed to do so.
* Form6Bad: the field descriptor to form a 6 from -1 failed to do so.
* Form10Bad: the field descriptor to form a 10 from -1 failed to do so.
* FormMinus2Bad: the field descriptor to form a -2 from -1 failed to do so.
* FormMinus3Bad: the field descriptor to form a -3 from -1 failed to do so.
* FormMinus4Bad: the field descriptor to form a -4 from -1 failed to do so.
* FormMinus5Bad: the field descriptor to form a -5 from -1 failed to do so.
* FormMinus6Bad: the field descriptor to form a -6 from -1 failed to do so.
* FormMinus7Bad: the field descriptor to form a -7 from -1 failed to do so.
* FormMinus10Bad: the field descriptor to form a -10 from -1 failed to do so.
* F356Bad: the field descriptor to put bits 0b-3b into bits 10b-13b failed to do so.
* Passed-EDTNF-Test: the system passed thru all the passes of EDTNF.
****************************************************************************************
****************************************************************************************
* Breakpoint Logic Analyzer Sync Points:
* ShouldHaveButDidnt: Control Store address 455
* ShouldntHaveButDid: Control Store address 452
* IntPBad1: Control Store address 502
* IntPBad: Control Store address 461
* Target377: Control Store address 3775
* WrongPlace: Control Store address 467
* CIAFailed: Control Store address 465
* APCFailed: Control Store address 463
* H2b8StuckLow: Control Store address 473
* H2b8StuckHigh: Control Store address 440
* FixVAbad: Control Store address 437
* Form2Bad: Control Store address 435
* Form4Bad: Control Store address 433
* Form5Bad: Control Store address 431
* Form6Bad: Control Store address 427
* Form10Bad: Control Store address 425
* FormMinus2Bad: Control Store address 423
* FormMinus3Bad: Control Store address 421
* FormMinus4Bad: Control Store address 413
* FormMinus5Bad: Control Store address 411
* FormMinus6Bad: Control Store address 407
* FormMinus7Bad: Control Store address 405
* FormMinus10Bad: Control Store address 403
* F356Bad: Control Store address 401
* Passed-EDTNF-Test: Control Store address 506
****************************************************************************************
%
****************************************************************************************
* INITIALIZATION:
TITLE[Test-New-Features];
********** R-registers: *************
RV[RStack,20];* temporary location for a stkp value
RV[TPage,21];* page field used to form a CSAddress value
RV[CSAddress,22];* control store address of target used to test NewInst feature
RV[Result,23];* used to hold a test result for checking
RV[ByteCode,24];* single-byte opcode used to test NextInst
RV[XPCF,25];* temporary location used to load PCF
RV[OriginalRefr,26];* used to store kernel’s REFR for later comparison
RV[ShouldBe, 27];* used by target to record target’s identity before returning
RV[FlagR,30];* holds flags to record whether or not task switches occurred
RV[AllOnes,31];* test word to get masked by the new field descriptors
RV[Revision,32,1];* revision number is 1 for this program
RV[Run-Time,33,4];* run time for this test is 4 seconds
RV[PassCount,34,0];* pass count for this program
RV[MaxPass,35,10000];* maximum number of passes for this run
****************************************************************************************
*** MAIN routine:
ONPAGE[1];
*Test the NewInst feature by calling instructions in locations 14 thru 17
* of page 15...1.
*A call should do a NewInst only if the page is 4...7 and the low two bits
* of the address are 01.
*No other instruction should modify SSTKP.
start:
go:RStack ← 377C;*initialize starting value for stkp
STKP ← RStack;*this value will never occur below
loadpage[4];
Callp[SetRet];*this call will set sstkp to the same value
RStack ← 20C;
TPage ← 16C;*initialize control store page number
TNILoop: TPage ← (TPage)-1;
goto[TestIntP, ALU=0]; *go to next test if pages 15...1 are done
T ← 17C;
T ← (lsh[Tpage,10]) or (T); *form control store address of first target instruction
CSAddress ← T;
TestNewInst:
RStack ← (RStack)+1;*comparison value for STKP
STKP ← RStack, call[.+2];*Set up return link for tested instruction
InstDone: T ← SSTKP, goto[ValCompare];*The target instruction will return to here.
*If a NewInst was done by the target instruction,
*T will contain RStack, otherwise not.
APC&APCTASK ← CSAddress;
RETURN;*notify target instruction
ValCompare:T ← (RStack) xor (T);
Result ← T;
T ← 1C;*test CSAddress. Bits 4,5 = 01 & 16,17 =01 mean
* that NewInst should have happened.
lu ← (ldf[CSAddress,4,2]) xor (T);*check top two bits of address
lu ← (ldf[CSAddress,16,2]) xor (T), dblgoto[TopIsOne, TopNotOne,ALU=0];
TopIsOne: lu ← Result, dblgoto[BottomIsOne, BottomNotOne,ALU=0];
TopNotOne: lu ← Result, goto[BottomNotOne];
BottomIsOne: dblgoto[ShouldHaveButDidnt, DidIt, ALU#0];
BottomNotOne: dblgoto[ShouldntHaveButDid, Didn’t, ALU=0];
ShouldHaveButDidnt: breakpoint, goto[DidIt];
ShouldntHaveButDid: breakpoint, goto[Didn’t];
DidIt: lu ← ldf[CSAddress,16,2], goto[ChkWrd];
Didn’t: lu ← ldf[CSAddress,16,2], goto[ChkWrd];
ChkWrd:CSAddress ← (CSAddress) - 1, dblgoto[TNILoop,TestNewInst,ALU=0];
*Test the IntPending branch condition by setting and clearing the bit,
*and verifying that the branch takes when it should, and doesn’t take when it shouldn’t.
TestIntP: T ← 10C; RS232 ← T;*set IntPending
dblgoto[IntPGood1,IntPBad1,IntPending];
IntPBad1: breakpoint, goto[TestIntP];*loop if bad
IntPGood1: T ← 0C; RS232 ← T;*Clear IntPending
dblgoto[IntPBad,IntPGood,IntPending];
IntPBad: breakpoint, goto[TestIntP];*loop if bad
IntPGood: goto[TestByteCode];*on to next test with IntPending = 0
*Test that instruction dispatching works properly. We dispatch to Opcode 200,100...4,2,1
*successively, checking that the dispatch works both in the presence and absence of a
*task switch (recall that the Kernel is running memory rerfresh). When we have
*checked all 8 bits of the dispatch, we set to go to opcode 377b, but set IntPending, and
*verify that control goes to opcode 0. NOTE: If this hardware doesn’t work, there is
*a good chance that analysis with the Logic Analyzer will be required, since the machine
*will probably go off the deep end.
TestByteCode: Result ← 377C;
STKP ← Result;*set STKP to point to REFR in Kernel, to check for task switch
ByteCode ← 400C;*initialize opcode number
XPCF ← 1C;*temporary register containing 1C
TryNextBit: ByteCode ← rsh[ByteCode,1], goto[TestH2Branch,R<0];
goto[TestIntPX,ALU=0], FlagR ← 3C;*tested all bits?
goto[KeepTrying];
TestIntPX: T ← 10C; *verify that IntPending sends control to Opcode 0 (2001b)
RS232 ← T; *set IntPending
ByteCode ← (ZERO) -1; *Dispatch will go to Target377 if this part of the test fails
KeepTrying: T ← STACK;*Kernel’s REFR
OriginalRefr ← T;
PCF ← XPCF; *point PCF at ByteCode
NEXTINST[ByteCode];
NIRET, T ← GETRSPEC[147];*Read CTASK,NCIA
CheckByteCode:lu ← (rhmask[ByteCode]) xor (T); *check ByteCode against constant from Target
goto[.+2, ALU=0];
WrongPlace: breakpoint;
ShouldBe ← lsh[ShouldBe,2];*format ShouldBe to the form stored in CIA
ShouldBe ← (ShouldBe) or (2000c);
T ← (Result) xnor (170000C);*CIA is read complemented
lu ← (ShouldBe) xor (T);
goto[.+2, ALU=0];
CIAFailed: breakpoint;*The thing in CIA was not what was expected
USECTASK;
T ← APC&APCTASK;
ShouldBe ← (ShouldBe) or (1C); *TPC should have 2001B or (ByteCode lsh 2)
lu ← (ShouldBe) xor (T);
goto[.+2, ALU=0];
APCFailed: breakpoint;*TPC[0] got the wrong value during the NIRET
*We want to test each bit in both the presence and in the absence of a task switch.
T ← OriginalRefr;
lu ← (STACK) xor (T);
dblgoto[SwitchHappened, NoSwitch, ALU#0]; *Refr is incremented by task 16
SwitchHappened:FlagR ← (FlagR) and not (1C), goto[CheckBothTypes];
NoSwitch:FlagR ← (FlagR) and not (2C), goto[CheckBothTypes];
CheckBothTypes: dblgoto[TryNextBit, KeepTrying, ALU=0];
*Test the branch on H2Bit8 by verifying that it branches when it should
*and doesn’t when it shouldn’t.
TestH2Branch: T ← 200C;dblgoto[TryOtherWay,H2b8StuckLow,H2Bit8];
H2b8StuckLow: breakpoint, goto[TestH2Branch];*loop if bad
TryOtherWay:T ← 0C;dblgoto[H2b8StuckHigh,TestNewFields,H2Bit8];
H2b8StuckHigh: breakpoint, goto[TestH2Branch];*loop if bad
*Test the new field descriptors (Misc board)
TestNewFields: Result ← 100c;
Result ← (Result) or (40000c); *desired result
AllOnes ← 200c;
AllOnes ← (AllOnes) or (100000c); *starting value
T ← (AllOnes), BS@[3], FZ@[341]; *FixVA
Result ← (Result) xor (T);
goto[.+2,ALU=0];
FixVAbad: breakpoint;
AllOnes ← (Zero) -1;
T ← 2c;
T ← (AllOnes) xor (T), BS@[3], FZ@[342]; *form 2 from AllOnes
Result ← T, goto[.+2, ALU=0];
Form2Bad: breakpoint;
T ← 4c;
T ← (AllOnes) xor (T), BS@[3], FZ@[343]; *form 4 from AllOnes
Result ← T, goto[.+2, ALU=0];
Form4Bad: breakpoint;
T ← 5c;
T ← (AllOnes) xor (T), BS@[3], FZ@[344]; *form 5 from AllOnes
Result ← T, goto[.+2, ALU=0];
Form5Bad: breakpoint;
T ← 6c;
T ← (AllOnes) xor (T), BS@[3], FZ@[345]; *form 6 from AllOnes
Result ← T, goto[.+2, ALU=0];
Form6Bad: breakpoint;
T ← 10c;
T ← (AllOnes) xor (T), BS@[3], FZ@[346]; *form 10 from AllOnes
Result ← T, goto[.+2, ALU=0];
Form10Bad: breakpoint;
(ShouldBe) ← 0C; *Temporary place for 0
T ← (2c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[347]; *form -2 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus2Bad: breakpoint;
T ← (3c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[350]; *form -3 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus3Bad: breakpoint;
T ← (4c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[351]; *form -4 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus4Bad: breakpoint;
T ← (5c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[352]; *form -5 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus5Bad: breakpoint;
T ← (6c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[353]; *form -6 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus6Bad: breakpoint;
T ← (7c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[354]; *form -7 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus7Bad: breakpoint;
T ← (10c);
T ← (Zero) - (T);
T ← (AllOnes) xor (T), BS@[3], FZ@[355]; *form -10 from AllOnes
Result ← T, goto[.+2, ALU=0];
FormMinus10Bad: breakpoint;
AllOnes ← 170000c;
T ← 360c;
T ← (AllOnes) xor (T), BS@[3], FZ@[356]; *This one puts bits 0-3 into bits 8d-11d
Result ← T, goto[.+2, ALU=0];
F356Bad: breakpoint;
PassCount ← (PassCount) + 1;*increment pass count
T ← MaxPass;
lu ← (PassCount) - (T);
goto[go,ALU<0];*finished all passes?
Passed-EDTNF-test: PassCount ← 0C, breakpoint, goto[go];
********************************************
OnPage[1];
return, AT[414];
return, AT[415];
return, AT[416];
return, AT[417];
********************************************
OnPage[2];
return, AT[1014];
return, AT[1015];
return, AT[1016];
return, AT[1017];
********************************************
OnPage[3];
return, AT[1414];
return, AT[1415];
return, AT[1416];
return, AT[1417];
********************************************
OnPage[4];
Target0: Result ← T, AT[2001]; *Special target for IntPending test.
ShouldBe ← 0C; *set up ShouldBe for comparison with CIA and TPC
loadpage[1];
gotop[CheckBytecode], T ← 377C; *original ByteCode was 377b
Target1: Result ← T, loadpage[1], AT[2005];
gotop[CheckBytecode], ShouldBe ← T ← 1C;
Target2: Result ← T, loadpage[1], AT[2011];
gotop[CheckBytecode], ShouldBe ← T ← 2C;
Target3: Result ← T, loadpage[1], AT[2021];
gotop[CheckBytecode], ShouldBe ← T ← 4C;
Target4: Result ← T, loadpage[1], AT[2041];
gotop[CheckBytecode], ShouldBe ← T ← 10C;
Target5: Result ← T, loadpage[1], AT[2101];
gotop[CheckBytecode], ShouldBe ← T ← 20C;
Target6: Result ← T, loadpage[1], AT[2201];
gotop[CheckBytecode], ShouldBe ← T ← 40C;
return, AT[2014];
SetRet:return, AT[2015];
return, AT[2016];
return, AT[2017];
********************************************
OnPage[5];
Target7: Result ← T, loadpage[1], AT[2401];
gotop[CheckBytecode], ShouldBe ← T ← 100C;
return, AT[2414];
return, AT[2415];
return, AT[2416];
return, AT[2417];
********************************************
OnPage[6];
Target8: Result ← T, loadpage[1], AT[3001];
gotop[CheckBytecode], ShouldBe ← T ← 200C;
return, AT[3014];
return, AT[3015];
return, AT[3016];
return, AT[3017];
********************************************
OnPage[7];
return, AT[3414];
return, AT[3415];
return, AT[3416];
return, AT[3417];
Target377: breakpoint, AT[3775];*IntPending did not send control to 2001b
nop;
loadpage[1];
goto[go];*loop to start of test
********************************************
OnPage[10];
return, AT[4014];
return, AT[4015];
return, AT[4016];
return, AT[4017];
********************************************
OnPage[11];
return, AT[4414];
return, AT[4415];
return, AT[4416];
return, AT[4417];
********************************************
OnPage[12];
return, AT[5014];
return, AT[5015];
return, AT[5016];
return, AT[5017];
********************************************
OnPage[13];
return, AT[5414];
return, AT[5415];
return, AT[5416];
return, AT[5417];
********************************************
OnPage[14];
return, AT[6014];
return, AT[6015];
return, AT[6016];
return, AT[6017];
********************************************
OnPage[15];
return, AT[6414];
return, AT[6415];
return, AT[6416];
return, AT[6417];
********************************************
end;