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*** *** *** *** <D0Diag>Rev-1>EDRMEx.mc Revision 1.1 May 3, 1980 *** *** *** ***
****************************************************************************************
*** EDRMEx.mc : R-register Memory Exerciser microcode
*** Purpose : This test exercises the R-registers. Only R-registers not occupied
by the program or the kernel are exercised.
*** Minimum Hardware : Standard 4 CPU boards.
*** Approximate Run Time : 4 seconds.
*** Obtained from CSL disk by Chuck Thacker, Dec 20,1979
*** Modified by : Chuck Thacker, December 18, 1978
Moved registers up to allow stackfaults to be checked
(if the fault is wired off so it can’t happen).
*** Modified by : Chuck Thacker, July 29, 1979
Added T test.
*** Modified by : T. Henning,Dec 20, 1979
Standardize title page and code format.
Implement looping and standard labels.
Added capability for all zeros, all ones, and checker patterns.
Deleted T test duplicated in EDSmallMem and covered more thoroughly there.
*** Modified by : Chuck Thacker, May 3, 1980
Standardized assembly with rmex.cm, fixed for new d0lang.
****************************************************************************************
****************************************************************************************
*SubTest Description:
* SubTest 1: writes a data pattern into each R-register, reads the contents back
and compares them with what was written.
* SubTest 2: reads each R-register and compares them with what was written.
****************************************************************************************
*BreakPoints:
* WORDBAD: Word rd0 read did not match wd0 written under mask md0, at the currentloc,
and in the corresponding SubTest.
* PASSED-EDRMEX-TEST: Passed all tests, and all passes.
****************************************************************************************
* ShortLoop Logic Analyzer Sync Points at Control Store address:
* WORDBAD:SubTest 1: Control Store address 411 at WRITELOOP1.
SubTest 2: Control Store address 443 at READLOOP1.
****************************************************************************************
*Special Reg. Definition:
* ShortLoop: At any breakpoint, the user has the choice of setting ShortLoop to a 1 to
loop on the current test. During the short loop, the user can modify the address
and data to the Control Store at will by changing CurrentLoc and Wd0, Wd1, and Wd2.
1, the current test will loop repeatedly for trouble shooting
0, no looping in current test
* PatternChoice:
Bit 15 - all zeros pattern, enable by 1, disable by 0
Bit 14 - all ones pattern, enable by 1, disable by 0
Bit 13 - checker pattern, enable by 1, disable by 0
Bit 12 - random pattern, enable by 1, disable by 0
Example: PatternChoice=1 enables the all zeros pattern only
PatternChoice=2 enables the all ones pattern only
PatternChoice=4 enables the checker pattern only
PatternChoice=10 enables the random pattern only
PatternChoice=17 enables all four of the patterns
PatternChoice=11 enables the random and all zeros patterns
* LoopControl: bit 0 & 15 are used to control the type of looping
bit 0 bit 15
0 0 write/read VARYing data at ONE address
0 1 write/read VARYing data at ALL address
1 0 write & check CONSTANT data at ONE address
1 1 write/read CONSTANT data at ALL address
Note that if the address is not allowed to increment, the program will stay in the write loop
forever. Also, during the read loop, it is not sensible to have LoopControl.0 =1, since a
different value was written into each cell during the write pass.
****************************************************************************************
*Subroutine Description:
* fillbuf: places a 16 bit number in wd0. The pattern can be all zeros, all ones,
checker, or random, depending on the users’ choice in CurrentPattern.
* rand: produces a pseudo-random number in t & xa registers
by Xa ← 4005*Xa + Ca mod 2**16.
* readRM: reads one word from R location currentloc into rd0, then compares
the results under the mask md0.
* writeRM: writes a word from wd0 to the R memory at currentloc.
****************************************************************************************
%
****************************************************************************************
*INITIALIZATION:
title[RM-Exerciser];
SET[ProgPage,1];*program is one page long
ONPAGE[ProgPage];
********** R-Registers: **********
RV[lowloc,20,50];*first location tested
RV[highloc,21,317];*last location tested
RV[currentloc,22];
RV[md0,23,177777];*1 word mask - 1’s mean compare the bit
RV[rd0,24];*1 word read buffer
RV[wd0,25];*1 word write buffer
RV[PatternChoice,26,17];*Enable all four pattern at program initialization
RV[PatternTry,27,1];*Initialize to all zeros pattern
RV[CurrentPattern,30,1];*Initialize to all zeros pattern
RV[Ones,31,177777];*define ones to be 177777
RV[Checker1,32,125252];*checker pattern register
RV[Checker0,33,052525];*checker pattern register
RV[Toggle,34,0];*checker toggle register
RV[ShortLoop,35,0];*initialize program at no short looping
RV[Revision,36,1];*REVISION 1
RV[Run-Time,37,4];*run time is about 4b or 4D seconds
RV[rlink0,40];*subroutine return link
RV[xa,41,123];*RNG registers
RV[ca,42,33031];
RV[savedXA,43];
RV[passcount,44,0];
RV[loopcontrol,45,1];
RV[maxpass,46,100];
RV[SubTest,47,0];
****************************************************************************************
*** MAIN routine:
start:
go:
passcount ← 0C;
Again:
t←xa;*save RNG
savedxa←t;
t←lowloc;*set address
currentloc←t;
NextPattern:
t ← (PatternTry) and not (17C);*what pattern to use?
goto[WhatPattern,alu=0];*exhausted all four pattern types?
PatternTry ← 1C;*yes, select the zero pattern again
Toggle ← 0C;*reset checker pattern toggle
PassCount← t ←(PassCount)+1;*increment pass count
t ← PassCount;
lu ← (maxpass) - (t);*done with all passes?
goto[Passed-EDRMEx-Test, alu<0];
goto[WhatPattern];
Passed-EDRMEx-Test:
call[rand], breakpoint;*precess the (not very good) RNG
goto[go];
WhatPattern:
t ← PatternChoice;*determine what pattern to use
t ← (PatternTry) AND (t);
goto[Next,alu=0];*do we want to use this pattern?
CurrentPattern ← t;*yes, use this pattern
PatternTry ← LSH[PatternTry,1], goto[writeloop0];
Next:PatternTry ← LSH[PatternTry,1], goto[NextPattern];*no, try the next pattern
*SUBTEST 1
SubTest ← 1C;
writeloop0: call[fillbuf];*generate data into write buffer
writeloop1:
call[writeRM],AT[411];*write it
call[readRM];*read and compare
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*short loop for trouble shooting?
goto[writeloop1];
t ← (loopcontrol) and (1C);
currentloc ← t ← (currentloc)+(t);*done?
lu←(highloc)-t;
goto[.+2, alu<0];
lu ← loopcontrol, dblgoto[writeloop1,writeloop0,R<0];*do not change data if loopcontrol.0=1
t←lowloc;*reset address
currentloc ← t;
t←savedxa;*reset RNG
xa←t;
*SUBTEST 2
SubTest ← 2C;
readloop0: call[fillbuf];*fill buffer
readloop1:
call[readRM],AT[443];*read and compare
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*short loop for trouble shooting?
goto[readloop1];
t ← (loopcontrol) and (1C);
currentloc ← t ← (currentloc)+(t);*done?
lu←(highloc)-t;
goto[.+2, alu<0];
lu ← loopcontrol, dblgoto[readloop1,readloop0,R<0];*do not change data if loopcontrol.0=1
call[rand];*precess the (not very good) RNG
goto[Again];
********** SUBROUTINE: fillbuf **********
*
*puts a 16-bit number into wd0. The pattern
*depends on the value of CurrentPattern:
*CurrentPatternWd0, Wd1Wd2
* 100000000All Zeros pattern
* 217777717All Ones pattern
* 412525212Checker pattern
*or 1252525or 05
* 10randomrandomRandom pattern
fillbuf: usectask;
t←apc&apctask;
rlink0 ← t;
t ← (CurrentPattern) AND (1C);
goto[Try1,alu=0];*want the zeros pattern?
wd0 ← 0C, goto[fbret];*yes, fill wd0 with zeros pattern
Try1: t ← (CurrentPattern) AND (2C);*no, try the ones pattern
goto[Try2,alu=0];*want the ones pattern?
t ← Ones;*yes, fill wd0 with ones pattern
wd0 ← t, goto[fbret];
Try2: t ← (CurrentPattern) AND (4C);*no, try the checker pattern
goto[Try3,alu=0];*want the checker pattern?
Toggle ← Toggle, goto[Checker01,R ODD];*yes, fill wd0 with checker pattern
t ← Checker1;*1010101010101010 pattern
wd0 ← t;
Toggle ← (Toggle) + 1, goto[fbret];*toggle checker pattern
Checker01: t ← Checker0; *0101010101010101 pattern
wd0 ← t;
Toggle ← (Toggle) + 1, goto[fbret];*toggle checker pattern
Try3: t ← (CurrentPattern) AND (10C);*no, try the random pattern
goto[fbret,alu=0];*want the random pattern?
call[Rand];*yes, fill wd0 with random pattern
wd0←t;
fbret:apc&apctask←rlink0;
return;
********** SUBROUTINE: rand **********
*
*to produce a pseudo-random number in t & Xa reg.
*formula: Xa ← 4005*Xa + ca mod 2**16
rand: t←xa;
t←(lsh[xa,2])+(t);*t← 5*xa
t←(lsh[xa,13])+(t);*t←4005*xa
t←(ca)+t;
xa←t,return;
********** SUBROUTINE: readRM **********
*
*reads one word from R location currentloc into RD0,
*then compares the results under the mask MD0.
*On error, the difference is in T.
readRM: stkp ← currentloc;
T ← stack;
RD0 ← t;
t←wd0;
t←(rd0) xor (t);
t←(md0) and (t);
goto[.+2,alu#0];
return;
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*short loop for trouble shooting?
return;
wordbad: breakpoint;
return;
********** SUBROUTINE: writeRM **********
*
*writes a word from WD0 to the R memory at currentloc.
writeRM: t← WD0;
stkp ← currentloc;
stack ← t;
return;
end;