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*** *** *** *** <D0Diag>Rev-1>EDCSEx.mc Revision 1.1 May 3, 1980 *** *** *** ***
****************************************************************************************
*** EDCSEx.mc : Control Store Exerciser microcode
*** Purpose : This test exercises the control store as a 4K x 36 bit memory.
Only locations not occupied by the program or the kernel are exercised.
*** Minimum Hardware : Standard 4 CPU boards.
*** Approximate Run Time : 30 seconds.
*** Written by : C. Thacker, Dec. 12, 1978
Added link saving to writeCS and readCSX to save link
smashed by control store operations.
*** Modified by : T. Henning, Oct. 5, 1979
Standardize title page and code format.
*** Modified by : T. Henning, Oct. 15, 1979
Implement looping and standard labels.
*** Modified by : T. Henning, Oct. 24, 1979
Added capability for all zeros, all ones, and checker patterns.
*** Modified by : C. Thacker, May 3, 1980
Standardized assemblw with csex.cm, changed for new d0lang
****************************************************************************************
****************************************************************************************
*SubTest Description:
* SubTest 0: writes a data pattern into each location, reads the contents back
and compares them with what was written.
* SubTest 1: reads each location and compares them with what was written.
****************************************************************************************
*BreakPoints:
* WORD0BAD: Word 0 of the Control Store read did not match word 0 written in SubTest0.
* WORD1BAD: Word 1 of the Control Store read did not match word 1 written in SubTest0.
* WORD2BAD: Word 2 of the Control Store read did not match word 2 written in SubTest0.
* WORD0BADREAD: Word 0 of the Control Store read did not match word 0 in SubTest1.
* WORD1BADREAD: Word 1 of the Control Store read did not match word 1 in SubTest1.
* WORD2BADREAD: Word 2 of the Control Store read did not match word 2 in SubTest1.
* Passed-EDCSEx-Test: Passed all tests, and all passes.
****************************************************************************************
* ShortLoop Logic Analyzer Sync Points at Control Store address:
* WORD0BAD: Control Store address 424 at TESTLOOP0.
* WORD1BAD: Control Store address 424 at TESTLOOP0.
* WORD2BAD: Control Store address 424 at TESTLOOP0.
* WORD0BADREAD: Control Store address 464 at TESTLOOP1.
* WORD1BADREAD: Control Store address 464 at TESTLOOP1.
* WORD2BADREAD: Control Store address 464 at TESTLOOP1.
****************************************************************************************
*Special Reg. Definition:
* ShortLoop: At any breakpoint, the user has the choice of setting ShortLoop to a 1 to
loop on the current test. During the short loop, the user can modify the address
and data to the Control Store at will by changing CurrentLoc and Wd0, Wd1, and Wd2.
1, the current test will loop repeatedly for trouble shooting
0, no looping in current test
* PatternChoice:
Bit 15 - all zeros pattern, enable by 1, disable by 0
Bit 14 - all ones pattern, enable by 1, disable by 0
Bit 13 - checker pattern, enable by 1, disable by 0
Bit 12 - random pattern, enable by 1, disable by 0
Example: PatternChoice=1 enables the all zeros pattern only
PatternChoice=2 enables the all ones pattern only
PatternChoice=4 enables the checker pattern only
PatternChoice=10 enables the random pattern only
PatternChoice=17 enables all four of the patterns
PatternChoice=11 enables the random and all zeros patterns
* LoopControl: bit 0 & 15 are used to control the type of looping
bit 0 bit 15
0 0 write/read VARYing data at ONE address
0 1 write/read VARYing data at ALL address
1 0 write & check CONSTANT data at ONE address
1 1 write/read CONSTANT data at ALL address
Note that if the address is not allowed to increment, the program will stay in the write loop
forever. Also, during the read loop, it is not sensible to have LoopControl.0 =1, since a
different value was written into each cell during the write pass.
****************************************************************************************
*Subroutine Description:
* FillBuf: places 2 16-bit patterns in WD0-1, and a 4 bit pattern in WD2.
The pattern may be all zeros, all ones, checker, or random,
depending on the value of CurrentPattern.
* Rand: produces a pseudo-random number in t & xa registers
by Xa ← 4005*Xa + Ca mod 2**16.
* ReadCSX: reads control store location CurrentLoc into RD0-2.
* WriteCS: writes 3 words from WD0-2 to the control store at CurrentLoc.
****************************************************************************************
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****************************************************************************************
*INITIALIZATION:
TITLE[Control Store Exerciser];
SET[ProgPage,1];*program is one page long
ONPAGE[ProgPage];
********** R-Registers: **********
RV[LowLoc,20,ADD[LSHIFT[ProgPage,10],400]]; *first location tested - one beyond program page
RV[CurrentLoc,21]; *the current Control Store location involved
RV[HighLoc,22,6777];*last location tested - below kernel
RV[Rd0,23];*3 word read buffer
RV[Rd1,24];
RV[Rd2,25];
RV[Wd0,26,177777];*3 word write buffer
RV[Wd1,27,177777];
RV[Wd2,30,17];
RV[Md0,31,177777];*3 word mask - 1’s mean compare the bit
RV[Md1,32,177777];
RV[Md2,33,17];
RV[Rlink0,34];*subroutine return link
RV[Xa,35,123];*Random Number Generator (RNG) registers
RV[Ca,36,33031];
RV[SavedXa,37];
RV[PassCount,40,0];
RV[MaxPass,41,100];
RV[SubTest,42];
RV[ShortLoop,43,0];*Disable looping at program initialization
RV[LoopControl,44,1];
RV[PatternChoice,45,17];*Enable all four pattern at program initialization
RV[PatternTry,46,1];*Initialize to all zeros pattern
RV[CurrentPattern,47,1];*Initialize to all zeros pattern
RV[Ones,50,177777];*define ones to be 177777
RV[Checker1,51,125252];*checker pattern register
RV[Checker0,52,052525];*checker pattern register
RV[Toggle,53,0];*checker toggle register
RV[Revision,54,1];*REVISION 1
RV[Run-Time,55,36];*Run-Time is 36b or 30D seconds
****************************************************************************************
*** MAIN routine:
start:
go: t←Xa;*save RNG
SavedXa←t;
t←LowLoc;*set address
CurrentLoc←t;
Again: t ← (PatternTry) and not (17C);*what pattern to use?
goto[WhatPattern,alu=0];*exhausted all four pattern types?
PatternTry ← 1C;*yes, select the zero pattern again
call[Rand];*process the (not very good) RNG
Toggle ← 0C;*reset checker pattern toggle
PassCount← t ←(PassCount)+1;*increment pass count
lu ← (MaxPass) - (t);
goto[.+2, alu>=0];*finished all passes?
Passed-EDCSEx-Test:PassCount ← 0C, goto[start], breakpoint;
nop;
WhatPattern: t ← PatternChoice;*determine what pattern to use
t ← (PatternTry) AND (t);
goto[NextPattern,alu=0];*do we want to use this pattern?
ThisPattern: CurrentPattern ← t, goto[.+2];*yes, use this pattern
NextPattern: PatternTry ← LSH[PatternTry,1], goto[Again];*no, try the next pattern
*SUBTEST 0
SubTest ← 0C;
writeloop0: Call[FillBuf];
writeloop1:nop;
TestLoop0:call[WriteCS];*write data into Control Store
call[ReadCSX];*read Control Store and store it in Rd0-2
t←Wd0, TASK;*allow mouse halt
t←(Rd0) xor (t);*compare Rd0 with Wd0 under mask Md0
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop0]; *short loop selected
t←(Md0) and (t);
goto[.+2,alu=0];
word0bad: breakpoint;
t←Wd1;*compare Rd1 with Wd1 under mask Md1
t←(Rd1) xor (t);
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop0];*short loop selected
t←(Md1) and (t);
goto[.+2,alu=0];
word1bad: breakpoint;
t←Wd2; *compare Rd2 with Wd2 under mask Md2
t←(Rd2) xor (t);
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop0];*short loop selected
t←(Md2) and (t);
goto[.+2,alu=0];
word2bad: breakpoint;
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop0];*short loop selected
t ← (LoopControl) and (1C);
CurrentLoc ← t ← (CurrentLoc)+(t);*done?
lu←(HighLoc)-t;
goto[.+2, alu<0];
lu ← LoopControl, dblgoto[writeloop1,writeloop0,R<0];
*do not change data if LoopControl.0=1
t←LowLoc;*reset address
CurrentLoc ← t;
t←SavedXa;*reset RNG
Xa←t;
Toggle ← 0C;*reset checker pattern toggle
*SUBTEST 1
SubTest ← 1C;
readloop0: call[FillBuf];*fill buffer
readloop1:nop;*odd-even placement constraints
TestLoop1:call[ReadCSX];*read Control Store and store it in Rd0-2
t←Wd0, TASK;*allow mouse halt
t←(Rd0) xor (t);*compare Rd0 with Wd0 under mask Md0
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop1];*short loop selected
t←(Md0) and (t);
goto[.+2,alu=0];
word0badRead: breakpoint;
t←Wd1;*compare Rd1 with Wd1 under mask Md1
t←(Rd1) xor (t);
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop1];*short loop selected
t←(Md1) and (t);
goto[.+2,alu=0];
word1badRead: breakpoint;
t←Wd2;*compare Rd2 with Wd2 under mask Md2
t←(Rd2) xor (t);
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop1];*short loop selected
t←(Md2) and (t);
goto[.+2,alu=0];
word2badRead: breakpoint;
ShortLoop ← ShortLoop, goto[.+2,R EVEN];*test for ShortLoop option
goto[TestLoop1]; *short loop selected
t ← (LoopControl) and (1C);
CurrentLoc ← t ← (CurrentLoc)+(t);*done?
lu←(HighLoc)-t;
goto[.+2, alu<0];
lu ← LoopControl, dblgoto[readloop1,readloop0,R<0];
*do not change data if LoopControl.0=1
PatternTry ← LSH[PatternTry,1], goto[start];*use the next pattern
********** SUBROUTINE: FillBuf **********
*
*puts pattern into Wd0, Wd1, Wd2. The pattern depends on the value
*of CurrentPattern:
*CurrentPatternWd0, Wd1Wd2
* 100000000All Zeros pattern
* 217777717All Ones pattern
* 412525212Checker pattern
*or 1252525or 05
* 10randomrandomRandom pattern
FillBuf: usectask;
t←apc&apctask;
Rlink0←t;
t ← (CurrentPattern) AND (1C);
goto[Try1,alu=0];*want the zeros pattern?
Wd0 ← 0C;*yes, fill Wd0-2 with zeros pattern
Wd1 ← 0C;
Wd2 ← 0C, goto[Bottom];
Try1: t ← (CurrentPattern) AND (2C);*no, try the ones pattern
goto[Try2,alu=0];*want the ones pattern?
t ← Ones;*yes, fill Wd0-2 with ones pattern
Wd0 ← t;
Wd1 ← t;
t ← (Ones) AND (17C);
Wd2 ← t, goto[Bottom];
Try2: t ← (CurrentPattern) AND (4C);*no, try the checker pattern
goto[Try3,alu=0];*want the checker pattern?
Toggle ← Toggle, goto[Checker01,R ODD];*yes, fill Wd0-2 with checker pattern
t ← Checker1;*1010101010101010 pattern
Wd0 ← t;
Wd1 ← t;
t ← (Checker1) AND (17C);
Wd2 ← t;
Toggle ← (Toggle) + 1, goto[Bottom];*toggle checker pattern
Checker01: t ← Checker0; *0101010101010101 pattern
Wd0 ← t;
Wd1 ← t;
t ← (Checker0) AND (17C);
Wd2 ← t;
Toggle ← (Toggle) + 1, goto[Bottom];*toggle checker pattern
Try3: t ← (CurrentPattern) AND (10C);*no, try the random pattern
goto[Bottom,alu=0];*want the random pattern?
call[Rand];*yes, fill Wd0-2 with random pattern
Wd0←t;
call[Rand];
Wd1←t;
call[Rand];
Wd2←t;
Wd2←(Wd2)and (17C);
Bottom: apc&apctask←Rlink0;
return;
********** SUBROUTINE: Rand **********
*
*to produce a pseudo-random number in t & Xa reg.
*formula: Xa ← 4005*Xa + ca mod 2**16
Rand: t←Xa;
t←(lsh[Xa,2])+(t);*t← 5*Xa
t←(lsh[Xa,13])+(t);*t←4005*Xa
t←(Ca)+t;
Xa←t,return;
********** SUBROUTINE: ReadCSX **********
*
*to read control store location CurrentLoc into RD0-2
ReadCSX: usectask;
t←apc&apctask;
Rlink0←t;
t←ZERO;
apc&apctask←CurrentLoc;
readCS;
t←csdata;
Rd0←t;
t←1C;
apc&apctask ← CurrentLoc;
readCS;
t←csdata;
Rd1←t;
t←3C;
apc&apctask ← CurrentLoc;
readCS;
t←csdata;
Rd2←t;
Rd2←(LDF[Rd2,0,4]);*control store bits come back in bits 0-3
apc&apctask←Rlink0;
return;
********** SUBROUTINE: WriteCS **********
*
*to write 3 words from WD0-2 to the control store at CurrentLoc.
WriteCS: usectask;
t←apc&apctask;
Rlink0←t;
t←Wd2;
lu←Wd0;
apc&apctask←CurrentLoc;
writeCS0&2;
lu←Wd1;
apc&apctask←CurrentLoc;
writeCS1;
apc&apctask←Rlink0;
return;
end;*to end the MAIN routine