//**************************************************************************************
//MISC9.TST
//By C. Thacker and M. Thomson  						October 6, 1978
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//(none)

//**************************************************************************************
//Test 16: Test the generation of MWX from MNBR and DBSB via proms b12, c12 (page 5), and c10 (page 6)

let Test16() be
[
	SpeakTest(16) //set initial conditions (see notes at end of MISC.TEST)

	//define busses for pins of prom c12 (page 5):
		//{c12msbaddr: c12p5,   c12p6,c12p7,c12p4}
		//{c12lsbaddr: c12p3,   c12p2,c12p1,c12p15}
		//{c12outputs: c12p12,  c12p11,c12p10,c12p9}


//PART 1: Check prom b12 and its input logic (page 5)

	{F2}=#33; //for loadMNBR

	//Check that prom b12 yields proper outputs for all input addresses

	for i = 0 to 31 do
	[
		{ALUA} = not i
		EClock() //clkMNBR': MNBR[0:15]_(ALUA[0:15]=i')

		let a = (i % (-(i rshift 4)))&#17 //i[12:15] if i<#20, else #17
		WCompare({c12msbaddr},a,16100,i) //prom b12 outputs
	]

	//Check that the g14 gate works properly

	for i = 0 to 10 do
	[
		{ALUA} = not (#100000 rshift i); //single "0" to MNBR[0:10]
		EClock() //clkMNBR': MNBR[0:15]_ALUA[0:15]
		WCompare({c12msbaddr},#17,16101,i) //result=0 => gate g14 output=0
	]


//PART 2: Check that prom c10 yields proper outputs for all input addresses (page 6)

	for i = 0 to 256 do //SB[2:5] and DB[2:5] will emerge =0
	[
		{ALUA} = i rshift 4
		{F2}=#25; //for loadSB 
		EClock() //SB[2:5]_(ALUA[12:15]=i[8:11])

		{ALUA}=i
		{F2}=#26; //for loadDB 
		EClock() //DB[2:5]_(ALUA[12:15]=i[12:15])

		//Define: "larger of two numbers (sb,db) - inverted"
		let tmw = valof //from "d0misc93427gen.bcpl" (prom c10)
		[
			let sb = i<<nibs.nib2
			let db = i<<nibs.nib3
			let x  = sb ge db?sb,db
			resultis  15-x
		]

		WCompare({c12lsbaddr},tmw,16200,i) //prom c10 outputs
	]


//PART 3: Check that prom c12 yields proper outputs for all input addresses (page 5)

	{F1}=#15; //for BBFBx'_0 when F1ok=1 to enable clkXLevel' 
	{R_PCXF'}=0; //for R[4:7]_MWX[0:3] when F2 not =#20

	for i = 0 to 255 do
	[
		//Set up prom c12 ms addr. bits = i[8:11] via prom b12
		{ALUA} = not (i rshift 4)
		{F2}=#33; //for loadMNBR 
		EClock() //MNBR[0:15]_(ALUA[0:15]=i[8:11]')

		//Set up prom c12 ls addr. bits (TMW[0:3]) = i[12:15] via prom c10
		//Since SB[2:5]=0 from prior logic, TMW[0:3] will =DB[2:5]'
		{ALUA} = not i
		{F2}=#66; //for loadDB; F1ok_1 for enable clkXLevel' later 
		EClock() //DB[2:5]_(ALUA[12:15]=i[12:15]')

		//Define: "smaller of two numbers (w1,w2)"
		let smx = valof //from "d0misc93427gen.bcpl" (prom c12)
		[
			let w1 = i<<nibs.nib2
			let w2 = i<<nibs.nib3
			resultis  w1 ls w2? w1,w2
		]

		WCompare({c12outputs},smx,16300,i) //prom c12 outputs (address =i)

		//Check MWX[0:3]_smx[0:3] and check the result via R[4:7].

		//Since F2=#66 (i.e. not = #20 or #60):
			//Rshift=0, and since R_PCXF'=0: R[4:7]_MWX[0:3]
			//clkDB' will occur insignificantly (redundant)

		EClock() //clkXLevel': MWX[0:3]_smx[0:3]

		//{mwxval: R.04,  R.05,R.06,R.07}
		WCompare({mwxval},smx,16301,i)
	]
]

//**************************************************************************************
//Test 17: SPARE

and Test17() be
[
	SpeakTest(17) //set initial conditions (see notes at end of MISC.TEST)
]