//**************************************************************************************
//MISC8.TST
//By C. Thacker and M. Thomson  						October 6, 1978
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//{Rsource: R_PCXF',R_DBSB',R_NBR',  F1ok,F2ok,F2.0,  F2.1,  F2.2,F2.3}

//**************************************************************************************
//Test 15: Test MNBR and DBSB (pages 5,6,7)

//Note: Certain irregular coding techniques are used during this test to reduce execution time.

let Test15() be
[
	SpeakTest(15) //set initial conditions (see notes at end of MISC.TEST)

	//{DBR: R.04,R.05,R.06,  R.07,R.08,R.09}
	//{SBR: R.10,R.11,R.12,  R.13,R.14,R.15}

//Test MNBR and DBSB load and read

	for i = 0 to 15 do
	[
		let x = 1 lshift i
		{ALUA}=x
		{F2}=#33; //loadMNBR
		EClock() //MNBR[0:15]_ALUA[0:15]
		{Rsource}=#620; //readMNBR
		WCompare({rbus},x,15000+i)
	]

	for i = 0 to 5 do
	[
		let x = 1 lshift i
		{ALUA}=x
		{F2}=#26; //loadDB
		EClock() //DB[0:5]_ALUA[10:15]
		{Rsource}=#520; //readDBSB
		WCompare({DBR},x,15100+i)
	]

	for i = 0 to 5 do
	[
		let x = 1 lshift i
		{ALUA}=x
		{F2}=#25; //loadSB
		EClock() //SB[0:5]_ALUA[10:15]
		{Rsource}=#520; //readDBSB
		WCompare({SBR},x,15200+i)
	]

//Test increment of MNBR by MWX (BBFA=> MNBR_ MNBR+MWX +1)

	for i = 0 to 15 do
	[
		for j = 0 to 15 do
		[
			{ALUA}=i
			{F2}=#33; //loadMNBR
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //MNBR[0:15]_(ALUA[0:15]=i)

			{ALUA}=j
			{F2}=#24; //loadCycleControl
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //MWX[0:3]_(ALUA[12:15]=j)

			//set up BBFA (loads MNBR with MNBR+MWX+1)
			{F1}=#20; //BBFA'_0, F2ok_0
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //MNBR[0:15]_((MNBR=i)+(MWX=j)+1)

			{Rsource}=#620; //R_NBR'_0, F2_#20 (Rshift=1), F1ok_0, F2ok_1
			WCompare({rbus},i+j+1,15300+i,j)
		]
	]

//Test increment of SB and DB by (MWX+1)

	{Rsource}=#520; //R_DBSB'_0, F2_#20, F1ok_0, F2ok_1
	//F1[0:3]=0 from prior logic (for BBFA'_0 when F1ok=1)

	for i = 0 to 15 do
	[
		{ALUA}=i
		{F2.1}=1; //for F2=#24: loadCycleControl
		{EdgeClockFeed'}=0
		{EdgeClockFeed'}=1; //MWX[0:3]_(ALUA[12:15]=i)

		let iplus1 = i + 1

		for j = 0 to 63 do
		[
			{ALUA}=j
			{F2.1}=1; {F2.3}=1; //for F2=#25: loadSB
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //SB[0:5]_(ALUA[10:15]=j)

			{F2.2}=1; {F2.3}=0; //for F2=#26: loadDB
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //DB[0:5]_(ALUA[10:15]=j)

			{F1ok}=1; {F2ok}=0; //BBFA'_0; DB_' _1
			{EdgeClockFeed'}=0
			{EdgeClockFeed'}=1; //SB _ SB+MWX+1, DB _ DB+MWX+1

			let sb = (iplus1 +j)&#77

			//Set up R[4:9]_DB[0:5], R[10:15]_SB[0:5]
			{F2}=#20; //F2_#20 (for RShift'_0), F1ok_0, F2ok_1
			WCompare({SBR},sb,15400+i,j)
			WCompare({DBR},sb,15500+i,j)
		]
	]

//Test bits [0:11] of the MNBR adder.
//Check one hex digit at a time, starting with bits [8:11].

	//Clear MWX so that MNBR will have exclusive control of carries
	{ALUA}=0
	{F2}=#24; //loadCycleControl
	EClock() //MWX[0:3]_(ALUA[12:15]=0)

	for i = 4 to 12 by 4 do
	[
		let p = #7777 rshift (12-i); //carry propagator

		for j = 0 to 15 do
		[
			let a = j lshift i

			{ALUA}=a; //place j in hex digit selected by i
			{F2}=#33; //loadMNBR
			EClock() //clkMNBR': MNBR_(ALUA=a)

			{Rsource}=#660; //R_NBR'_0, F2_#20 (Rshift=1), F1ok_1 (BBFA'_0)
			EClock() //clkMNBR': MNBR_(MNBR+1)
			WCompare({rbus},a+1,15600+i,j)

			{ALUA} = a % p; //propagate carry into hex digit selected by i
			{F2}=#33; //loadMNBR
			EClock() //clkMNBR': MNBR_(ALUA=a%p)

			{Rsource}=#660; //R_NBR'_0, F2_#20 (Rshift=1), F1ok_1 (BBFA'_0)
			EClock() //clkMNBR': MNBR_(MNBR+1)
			WCompare({rbus},(j+1) lshift i,15700+i,j)
		]
	]

//Test BBDisp.0, BBDisp.1, BBDisp.2 (pages 5,6)

	//{BBDisp: BBDisp.0,BBDisp.1,BBDisp.2}

	let BBsb = table [ 3;3;3;3; 7;6;5;4 ]

	//The following loop causes: BBDisp.0_i[13], SBLast_i[14], DBLast_i[15]

	for i = 0 to 7 do
	[
		{ALUA} = i lshift 13
		{F2}=#33; //loadMNBR
		EClock() //MNBR_(ALUA=i lshift 13), hence BBDisp.0=i[13]

		{ALUA} = -1 * ((i rshift 1)&1)
		{F2}=#25; //loadSB
		EClock() //SB_(ALUA=-1) if i[14]=1 (else 0), hence SBLast=i[14]

		{ALUA} = -1 * (i&1)
		{F2}=#26; //loadDB
		EClock() //DB_(ALUA=-1) if i[15]=1 (else 0), hence DBLast=i[15]

		WCompare({BBDisp},BBsb!i,15800+i)
	]
]