//************************************************************************************** //MISC7.TST //By C. Thacker and M. Thomson February 16, 1979 //Sub Test Program for D0 MISC Module //************************************************************************************** get "misc.d" //Edge pin signal busses used by all MISC test modules: //{ALUA: ALUA.00, ALUA.01,ALUA.02,ALUA.03, ALUA.04,ALUA.05,ALUA.06, ALUA.07,ALUA.08,ALUA.09, ALUA.10,ALUA.11,ALUA.12, ALUA.13,ALUA.14,ALUA.15} //{F1: F2ok,F1ok,F1.0, F1.1,F1.2,F1.3} //{F2: F1ok,F2ok,F2.0, F2.1,F2.2,F2.3} //{rbus: R.00, R.01,R.02,R.03, R.04,R.05,R.06, R.07,R.08,R.09, R.10,R.11,R.12, R.13,R.14,R.15} //************************************************************************************** //Edge pin signal busses and manifests used by this particular MISC test module: //{CYCOUNT: CYCOUNT.0, CYCOUNT.1,CYCOUNT.2,CYCOUNT.3} //{NCYCOUNT: CYCOUNT.0', CYCOUNT.1',CYCOUNT.2',CYCOUNT.3'} //{F1F2: F1.0,F1.1, F1.2,F1.3,F2.0, F2.1,F2.2,F2.3} //{MASK: MASK.00, MASK.01,MASK.02,MASK.03, MASK.04,MASK.05,MASK.06, MASK.07,MASK.08,MASK.09, MASK.10,MASK.11,MASK.12, MASK.13,MASK.14,MASK.15} //************************************************************************************** //Test 13: SPARE let Test13() be [ SpeakTest(13) //set initial conditions (see notes at end of MISC.TEST) ] //************************************************************************************** //Test 14: Check MASKS and CYCLE COUNT values (pages 3,4,8) and Test14() be [ SpeakTest(14) //set initial conditions (see notes at end of MISC.TEST) //Set up initial conditions: {BSEL.1}=1; //for SF'_0 when BSEL.0=1 {Cycle0Feed'}=0; //clocks will be Cycle0 except where noted //MemInst-a =0 from SpeakTest for i = 0 to 255 do [ {ALUA}=i //short fields off {BSEL.0}=0; //for SF'=1 //Load SB {F2}=#25; //F1ok_0, F2ok_1, SB_' _0 ClockCycle1() //clkSB' active: SB[0:5]_(ALUA[10:15]=i[10:15]) //Load CycleControl: load DBX and MWX, advance SB into SBX {F2.3}=0; //for F2=#24: CycleControl_' _0 ClockCycle1() //clkXLevel' active: //DBX[2:5]_(ALUA[8:11]=i[8:11]), [DBX[0:1]_DB[0:1]=??..don't care] //SBX[2:5]_(SB[2:5]=i[12:15]), [SBX[0:1]_SB[0:1]=i[10:11]..don't care] //MWX[0:3]_(ALUA[12:15]=i[12:15] //test WFA {F1}=#31; //F1ok_1, F2ok_0, WFA'_0, WFBBFA'_0 EClock() //MASK[0:15]_MS[0:15]_proms i13,g12,c7,e7 //CYCOUNT[0:3]_cx[0:3]_prom g10 WCompare({MASK},not WFBBFBMask(i),14000,i) WCompare({CYCOUNT},WFACount(i),14001,i) WCompare({NCYCOUNT},(not WFACount(i)),14002,i) //test BBFA {F1}=#20; //BBFA'_0, WFBBFA'_0 EClock() //MASK[0:15]_MS[0:15]_proms i13,g12,c7,e7 //CYCOUNT[0:3]_cx[0:3]_prom f10 WCompare({MASK},not WFBBFBMask(i),14003,i) WCompare({CYCOUNT},BBFACount(i),14004,i) //test WFB {F1}=#33; //WFB'_0, WFBBFB'_0 EClock() //MASK[0:15]_MS[0:15]_proms i14,h13,c8,d7 //CYCOUNT[0:3]_cx[0:3]_f11 gates =0 WCompare({MASK},WFBBFBMask(i),14005,i) WCompare({CYCOUNT},0,14006) //test BBFB {F1.3}=0; //for F1=#32: BBFB'_0, WFBBFB'_0 EClock() //MASK[0:15]_MS[0:15]_proms i14,h13,c8,d7 //CYCOUNT[0:3]_cx[0:3]_f11 gates =0 WCompare({MASK},WFBBFBMask(i),14007,i) WCompare({CYCOUNT},0,14008,i) //test RF {F1}=#34; //RF'_0 EClock() //MASK[0:15]_MS[0:15]_proms h12,b8 //CYCOUNT[0:3]_cx[0:3]_prom g11 WCompare({MASK},RFMask(i),14009,i) WCompare({CYCOUNT},RFCount(i),14010,i) //Check that ShortFldDisp'=1 while SF=0 WCompare({ShortFldDisp'},1,14011,i) //SF'=1 //test SF {BSEL.0}=1; //SF'_0 {F1ok}=0; //for RF'=1 {F1F2}=i WCompare({ShortFldDisp'},Promg9p12(i),14012,i) //SF'=0 EClock() //MASK[0:15]_MS[0:15]_proms i11,h11,e9,e8 //CYCOUNT[0:3]_cx[0:3]_prom f9 WCompare({MASK},SFMask(i),14013,i) WCompare({CYCOUNT},SFCount(i),14014,i) ] //test Noop count and mask {BSEL.0}=0; //SF'_1 EClock() //MASK[0:15]_MS[0:15]_g13,b9 gates =0 //CYCOUNT[0:3]_cx[0:3]_f11 gates =0 WCompare({MASK},0,14020) WCompare({CYCOUNT},0,14021) //test NextInst mask with IntPending=0 {H2.12}=0 {F1}=#21; //enable RS232_H2 ClockCycle1() //IntPending_(H2.12=0) {F1}=#36; //F1ok_1, F2ok_0, NextInst'_0, NextInstOp'_0 EClock() //MASK[0:15]_MS[0:15]_g13,b9 gates =#176003 WCompare({MASK},#176003,14022) //test NextInst mask with IntPending=1 {H2.12}=1 {F1}=#21; //enable RS232_H2 ClockCycle1() //IntPending_(H2.12=1) {F1}=#36; //F1ok_1, F2ok_0, NextInst'_0, NextInstOp'_0 EClock() //MASK[0:15]_MS[0:15]_g13,b9 gates =#177777 WCompare({MASK},#177777,14023) //test NextOp mask {F1.3}=1; //for F1=#37: NextOp'_0, NextInstOp'_0 EClock() //MASK[0:15]_MS[0:15]_g13,b9 gates =#177400 WCompare({MASK},#177400,14024) //test cycle count for NextInst/NextOp //first, load PCF with 0 (a8 ff's, page 8) {ALUA}=0 {F2}=#74; //F1ok_1, F2ok_1, PCF'_0 ClockCycle1() //PCF[0:3]_(gnd, ALUA[13:15]=0) //F1=#77 (same as #37 above, but F2ok=1): NextInst'_1 EClock() //CYCOUNT[0:3]_cx[0:3]_f11 gates =#10 WCompare({CYCOUNT},#10,14025) {F1.3}=0; //for F1=#36: NextInst'_0 EClock() //CYCOUNT[0:3]_cx[0:3]_f11 gates =#12 (PCF.3=0 => cx.0=1) WCompare({CYCOUNT},#12,14026) //PCF_1 (F2 still =#74 for loading PCF) {ALUA.15}=1 ClockCycle1() //PCF[0:3]_(gnd, ALUA[13:15]=1) EClock() //CYCOUNT[0:3]_cx[0:3]_f11 gates = #2 (PCF.3=1 => cx.0=0) WCompare({CYCOUNT},2,14027) ] and WFBBFBMask(i) = valof [ let RightTab = table [ #177777;#077777;#037777;#017777; #007777;#003777;#001777;#000777; #000377;#000177;#000077;#000037; #000017;#000007;#000003;#000001 ] let LeftTab = table [ #100000;#140000;#160000;#170000; #174000;#176000;#177000;#177400; #177600;#177700;#177740;#177760; #177770;#177774;#177776;#177777 ] let fb = i<