//**************************************************************************************
//MISC6.TST
//By C. Thacker and M. Thomson  						February 16, 1979
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//{H2.0812: H2.08,H2.09,  H2.10,H2.11,H2.12}

//Test clip from location h7 to tester socket "D":

	//{promh7in: RingState.0',RingState.1',  RingState.2',RingState.3',TestBit,  RingDat.0',WakePending,RingDat=0'}

	//{promh7out: Sample,  Send,SetWake,SetCarry}

//**************************************************************************************
//Test 12: Test the RS232 Interface logic (pages 14,15)
//         Test the TestBit multiplexor (page 12)
//         Test the i7, i6, and h7 proms (page 12)
//         Test miscellaneous Timer logic not checked elsewhere

let Test12() be
[
	SpeakTest(12) //set initial conditions (see notes at end of MISC.TEST)

//This test requires the following test connector:
	//25-pin female D-shell connector (RS232 interface - page 15)
	//	The connector is wired as follows:
	//	 2 ->  3        (TData -> RcvData)
	//	 4 ->  5        (ReqSend -> CTS)
	//	11 ->  6,15     (RS232SpareOut1 -> DSRdy,TXClockIn)
	//	20 ->  8,17,22  (DTermRdy -> CarrierDetect,RCVClockIn,RingIndicator)

//Initialization:

	//RUN=0 during SpeakTest caused: Phase0_1, WakeRq_0, NewCmd_1
	//F2=0 from SpeakTest (hence Rshift=0 since F2 not =#20); also, Cycle0=0

	ClockCycle0() //TimerDly_(R_Timer =0) for a10b gate output =1 (page 11) (for WakeRq hold)

//Set up conditions to permit use of the RamCyc() routines (listed at end of this test):

	{F1}=#22; //TLoad'_0 for enable clkTimer' and NewCmd_1

	RClock() //Phase0=1
	         //ReadClk' : (dlyLoadAdd_(LoadAdd=?) - don't care)
	         //           LoadAdd_0 (since Ph0=0)
	         //RamClock': NewCmd_1 (since TLoad'=0 and GoCycle1=1)

	RClock() //Phase3=1 (RingWrt' will occur if dlyLoadAdd=1, but is insignificant)

	RClock() //Phase2=1
	         //ReadClk' : dlyLoadAdd_(LoadAdd=0)
	         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
	         //RamClock': Phase1_1


//PART 1: Test the five RS232 Interface logic bits which are
//        loaded from H2[8:12] and displayed by R[9:11],SetTime,IntPending (page 10)
//        Test the Rclk and Tclk inputs to the TestBit mux (page 12)

	//Enable the f3 gates feeding r[8:15] (page 15)
	{R_NBR'}=0; //RShift=0 since F2ok=0 from SpeakTest (page 8)

	for i = 0 to 4 do
	[
		let a = 1 lshift i
		{H2.0812}=a

		{F1}=#21; //enable RS232_H2 for clkRS232' when EdgeClock.GoCycle1 (page 8,9)
		EClock() //clkRS232': g3 ff's _ (H2.0812=a) (page 15)
		{F1}=#22; //TLoad'_0 for enable clkTimer' and NewCmd_1

		//{t12bus0: R.09,R.10,  R.11,SetTime,IntPending}
		WCompare({t12bus0},a,12000+i) //H2[8:12]

		WCompare({R.12},(8 rshift i)&1,12001,i) //R.12=Tclk=H2.09
		WCompare({R.13},(4 rshift i)&1,12002,i) //R.13=Rclk=H2.10
		WCompare({R.15},(4 rshift i)&1,12003,i) //R.15=H2.10

		//Check TestBit = Rclk (pages 12,15) (RingState[0:1]'=0)
		RamCycA(#140000) //for RingState[0:1]'_0, using LAddr[0:3]=0
			//routine has 2 ReadClock's: i3g ff _ i3f ff _ (Rclk=H2.10)
		//Check RingState[0:1]'=0; check TestBit=Rclk=1 when i=2, else 0
		WCompare({promh7in}&#310,(2 lshift i)&8,12020+i)

		//Check TestBit = Tclk (pages 12,15) (RingState[0:1]'=1)
		RamCycA(#100000) //for RingState[0:1]'_1, using LAddr[0:3]=0
			//routine has 2 ReadClock's: i3i ff _ i3h ff _ (Tclk=H2.09)
		//Check RingState[0:1]'=1; check TestBit=Tclk=1 when i=3, else 0
		WCompare({promh7in}&#310,#100 % ((1 lshift i)&8),12040+i)
	]


//PART 2: Test R.08_RS232InBit_Rdat_(RcvData_TData)_RS232OutBit_NextBitToGo_H2.15 (pages 14,15)
//        Test the Rdat input to the TestBit mux (page 12)
//        RamCycB() routines are used in places to avoid RS232OutBit_1 from RUN=0 in RamCycA()

	//RA[0:3]=1 from previous tests

	for i = 0 to 1 do
	[
		{H2.15}=i
		{F1}=#21; //enable RS232_H2 for clkRS232' when EdgeClock.GoCycle1 (page 8,9)
		EClock() //clkRS232': NextBitToGo_(H2.15=i) (page 15)
		{F1}=#22; //TLoad'_0 for enable clkTimer' and NewCmd_1
 
		//Set the prom h7 address = 0011 xxx0 for Send=1
		let a = #140002 % (4*i)
		RamCycA(a) //RingState[0:3]'_3, RingDat[0:7]'_#377 (for RingDat=0'=0)
		           //RamAddr[0:3]_LAddr[0:3]_4i+2
		WCompare({promh7in}&#361,#60,12100+i)
		WCompare({Send},1,12102+i)

		RamCycB()  //Phase1: RA[0:3]_(RA[0:3]=4i+1)+1 (2,6)
		           //Phase0: read "Send" code from RA[0:3]=4i+2
		           //Phase2: RS232OutBit_(NextBitToGo=i) (page 14)
		           //(Rdat=RcvDat'=TData'=RS232OutBit=i) (page 15)

		//Check that TData'=RS232OutBit=i (via R.14)
		WCompare({R.14},i,12104+i) //R.14=TData'=i

		//Check TestBit = (Rdat=i) (pages 12,15) (RingState[0:1]'=2)
		{ALUA} = #40000
		EClock() //for LState[0:3]_1, LAddr[0:3]_0
		RamCycB()  //Phase1: RA[0:3]_(RA[0:3]=4i+2)+1 (3,7)
		           //Phase2: RingState[0:1]'_2, using LAddr[0:3]=0
			//routine has 2 ReadClock's: i4g ff _ i4f ff _ (Rdat=RS232OutBit=i)
		//Check RingState[0:1]'=2; check TestBit=Rdat=RS232OutBit=i
		//WCompare({promh7in}&#310,#200 % (i lshift 3),12110+i)

		//Set the prom h7 address = 0010 xxx0 for Sample=1
		{ALUA} = #150005 + (4*i)
		EClock() //for LState[0:3]_#15, LAddr[0:3]_4i+5
		RamCycB()  //Phase1: RA[0:3]_(RA[0:3]=4i+3)+1 (4,8)
		           //Phase3: write "Sample" code
		           //Phase2: read "Sample" code
		WCompare({promh7in}&#361,#40,12120+i)
		WCompare({Sample},1,12122+i)

		RamCycB()  //Phase1: RA[0:3]_(RA[0:3]=4i+4)+1 (5,9)
		           //Phase0: read "Sample" code from RA[0:3]=4i+5
		           //Phase2: RS232InBit_(Rdat=i) (page 14)
		WCompare({R.08},i,12130+i) //R.08=RS232InBit=i

		//Check that RUN=0 D.C. sets RS232OutBit
		RamCycA(#40000) //Phase1: RUN=0 => RS232OutBit_1
		           //Phase2: RingState[0:1]'_2, using LAddr[0:3]=0
			//routine has 2 ReadClock's: i4g ff _ i4f ff _ (Rdat=RS232OutBit=1)
		//Check RingState[0:1]'=2; check TestBit=Rdat=RS232OutBit=1
		//WCompare({promh7in}&#310,#210,12140+i)
	]

	//Increment RA[0:3] from 9 to 0 to simplify tests to follow
	for i = 0 to 6 do [ RamCycB() ]


//PART 3: Test the Carry logic (pages 12,13)
//        Test the Carry input to the TestBit mux (page 12)

	//Check that SetCarry=0 with prom h7 address = 1011 x1x0 (from prior test)
	WCompare({promh7in}&#365,#264,12200)
	WCompare({SetCarry},0,12201)

	//Check TestBit = Carry=0 (pages 12,13) (RingState[0:1]'=3)
	RamCycA(0) //for RingState[0:1]'_3, using LAddr[0:3]=0
	           //Phase0: read "SetCarry=0" code from RA[0:3]=0
	           //Phase2: Carry_(SetCarry=0) (pages 12,13)
	//Check RingState[0:1]'=3; check TestBit=Carry=0
	//WCompare({promh7in}&#310,#300,12202)

	//Set the prom h7 address = 0110 xxx0 for SetCarry=1
	//RamCycA(#110000) //RingState[0:3]'_6, RingDat[0:7]'_#377 (for RingDat=0'=0)
	                 //RamAddr[0:3]_LAddr[0:3]_0, (RA[0:3] also =0)
	//WCompare({promh7in}&#361,#140,12203)
	//WCompare({SetCarry},1,12204)

	//Check TestBit = Carry=1 (pages 12,13) (RingState[0:1]'=3)
	RamCycA(0) //for RingState[0:1]'_3, using LAddr[0:3]=0
	           //Phase0: read "SetCarry=1" code from RA[0:3]=0
	           //Phase2: Carry_(SetCarry=1) (pages 12,13)
	//Check RingState[0:1]'=3; check TestBit=Carry=1
	//WCompare({promh7in}&#310,#310,12205)


//PART 4: Check the codes in proms i7, i6, and h7 (page 12)

	//Table of prom outputs (i7,,i6,,h7):
	//DecrRing',, WState[0:3],, Sample,Send,SetWake,SetCarry

	let t12sb1 = table [

	#740;#740;#740;#740; #740;#740;#740;#740; #760;#760;#760;#760; #760;#760;#760;#760;
	#740;#740;#740;#740; #740;#740;#740;#740; #430;#430;#430;#430; #430;#430;#430;#430;
	#212;#202;#330;#320; #330;#320;#330;#320; #212;#202;#330;#320; #330;#320;#330;#320;
	#206;#202;#304;#300; #304;#300;#304;#300; #206;#202;#304;#300; #304;#300;#304;#300;

	#660;#660;#660;#660; #660;#660;#660;#660; #640;#640;#640;#640; #640;#640;#640;#640;
	#424;#424;#424;#424; #424;#424;#424;#424; #640;#640;#640;#640; #640;#640;#640;#640;
	#221;#220;#221;#220; #221;#220;#221;#220; #221;#220;#221;#220; #221;#220;#221;#220;
	#200;#200;#200;#200; #200;#200;#200;#200; #200;#200;#200;#200; #200;#200;#200;#200;

	#620;#620;#620;#620; #620;#620;#620;#620; #560;#560;#560;#560; #560;#560;#560;#560;
	#720;#720;#720;#720; #720;#720;#720;#720; #540;#540;#540;#540; #540;#540;#540;#540;
	#202;#202;#120;#120; #120;#120;#120;#120; #202;#202;#120;#120; #120;#120;#120;#120;
	#500;#500;#500;#500; #500;#500;#500;#500; #500;#500;#500;#500; #500;#500;#500;#500;

	#502;#502;#460;#460; #460;#460;#460;#460; #112;#102;#070;#060; #070;#060;#070;#060;
	#502;#502;#440;#440; #440;#440;#440;#440; #106;#102;#044;#040; #044;#040;#044;#040;
	#502;#502;#420;#420; #420;#420;#420;#420; #102;#102;#020;#020; #020;#020;#020;#020;
	#400;#400;#400;#400; #400;#400;#400;#400; #001;#000;#001;#000; #001;#000;#001;#000 ]


	//RA[0:3]=0 from previous tests, but will increment 1024 times
	//during this test and emerge =0 again


	for i = 0 to 1 do
	[
		//Set up Rclk, Tclk, and NextBitToGo to each =i so TestBit will =i later

		//Put the value of i in all g3 ff's (page 15)
		{H2.0812} = -i; //Rclk and Tclk will each =i
		{H2.15} = i; //NextBitToGo will =i (and Rdat will =i later)

		{F1}=#21; //enable RS232_H2
		EClock() //clkRS232': g3 ff's _ 1's if i=1, else 0's
		{F1}=#22; //TLoad'_0 for enable clkTimer' and NewCmd_1

		//Partial set up for SetCarry=i during j loop
		let c = #110022 xor (i lshift 4) //#110022 if i=0, #110002 if i=1

		for j = 0 to 127 do
		[
 			let a = (j lshift 2)&#14 //partial address for LAddr[0:3]

			//RA[0:3] = a (0 mod 4) at this point

			//SetWake_j[15]
			let wa = #50000 % ((j&1) lshift 11) % a
			RamCycA(wa) //RA[0:3] does NOT increment (stays =a)
			            //RUN101(): WakeRq_0, RS232OutBit_1
			            //Phase2: WakePending_(WakeRq=0) for prom h7 address bit
			WCompare({SetWake},j&1,12300+i,j) //prom h7 addr: 1010,,x,j[15]',0,x

			//Send_1 for RS232OutBit_(NextBitToGo=i)
			let sa = #140001 % a
			RamCycA(sa) //RA[0:3] does NOT increment (stays =a)
			            //RUN101(): WakeRq_0, RS232OutBit_1
			            //Phase2: WakeRq_(SetWake=j[15])
			            //then WakeRq_WakeRq since gate a10b output =1 (page 11)
			//WCompare({Send},1,12310+i,j) //prom h7 addr: 0011,,xxx0

			//SetCarry_i
			{ALUA} = c % a; //find c in i loop
			EClock() //clkTimer': LState[0:3]_#11
			         //           LDat[0:7]  _(1 if i=0, 0 if i=1) for RingDat=0 if i=1
			         //           LAddr[0:3] _a%2
 			RamCycB() //Phase1: RA[0:3]_(RA[0:3]=a)+1 (1,5,#11,#15) 
			//#1      //Phase2: RS232OutBit_(NextBitToGo=i), hence Rdat=i (pages 14,15)
			//WCompare({SetCarry},i,12320+i,j) //prom h7 addr: 0110,,xxxi

			//Write j pattern; set up write control for RamCycB()'s #3 and #4
			let jpat = ((j&#174) lshift 9) % ((j&2) lshift 3)
			{ALUA} = jpat % a % 3
			EClock() //clkTimer': LState[0:3]_j[9:12]
			         //           LDat[0:7]  _j[13],,000000,,j[14]
			         //           LAddr[0:3] _a%3
			{F1ok}=0; //TLoad'_1 for dlyLoadAdd_LoadAdd_NewCmd_0 
 			RamCycB() //Phase1: RA[0:3]_(RA[0:3]=a%1)+1 (2,6,#12,#16)
			//#2      //Phase0: NewCmd_0 since TLoad'=1 and (Phase0.Loadadd)=1
			          //Phase3: write j pattern into address = LAddr[0:3]=a%3
			          //Phase2: RingState[0:3]'_j[9:12]'
			          //        RingDat[0:7]'  _j[13]',,111111,,j[14]'
			          //        RingDat=0'_(j[13]%j[14])
			          //        WakePending_(WakeRq=j[15])
			          //        Carry_(SetCarry=i) for TestBit=i (Rclk=Tclk=Rdat=i)
			          //        LoadAdd_(NewCmd=0) (initiated by TLoad'=1)

			//Check the address that should be on proms i7,,i6,,h7:
			let k = j xor #174
			let d = ((k lshift 1)&#362) % (i lshift 3) % (k&4) % j<<w.b13 % j<<w.b14
			//WCompare({promh7in},d,12330+i,j)

			//Code for prom i7,,i6,,h7 outputs at address d:
			//DecrRing',, WState[0:3],, Sample,Send,SetWake,SetCarry
			let e = t12sb1!d

			//Check the outputs from prom h7 (Sample,Send,SetWake,SetCarry)
			//WCompare({promh7out},e&#17,12340+i,j)

			//Check the DecrRing' signal:
			//WCompare({DecrRing'},e rshift 8,12350+i,j)

			//Read and modify j pattern for write in RamCycB() #4
 			RamCycB() //Phase1: RA[0:3]_(RA[0:3]=a%2)+1 (3,7,#13,#17)
			//#3      //Phase0: dlyLoadAdd_(LoadAdd=0) (initiated by TLoad'=1)
			          //        re-read j pattern from RA[0:3]=a%3
 			          //Phase3: (RingWrt' is inactive since dlyLoadAdd=0)
			          //Phase2: g4 ff's _ (WState[0:3] = prom i6 outputs)
			          //        g4,i4 ff's _ (WDat[0:7] =
			          //            (RingDat=j[13],,000000,,j[14]) + (LDat=DecrRing))
			          //        i4i ff _0 since dlyLoadAdd=0 (page 13)
			          //        i4i ff =0 enables Phase1 write in RamCyc() #4 

			//Restore controls to resume Phase3 writes after RamCycB() #4
			{F1ok}=1; //TLoad'_0 for LoadAdd_NewCmd_1

			//Write, then read modified j pattern to test proms i7 and i6
 			RamCycB() //Phase1: write g4,i4 ff's into address = RA[0:3]=a%3
			//#4      //        RA[0:3]_(RA[0:3]=a%3)+1 (4,#10,#14,0)
			          //        NewCmd_1 since TLoad'=0 
			          //Phase3: (RingWrt' is inactive since dlyLoadAdd=0)
			          //Phase2: Read Phase1 write data from LAddr[0:3]=a%3:
			          //            RingState[0:3]' gets previous prom i6 data 
			          //            RingDat[0:7]' gets previous RingDat,DecrRing data
			          //        LoadAdd_(NewCmd=1) (resume Phase3 writes)

			//Check prom i6,i7 results: RingState[0:3]',,x,RingDat.0',x,RingDat=0'

			let t12sb2 = table [ 1;4;4;5; 5;1;1;1 ]
			let f = (j&6) % (e rshift 8) //address for table t12sb2
			let g = ((not e)&#360) % t12sb2!f

			//WCompare({promh7in}&#365,g,12360+i,j)
		]
	]


//PART 5: Check the WakeP3' and WakeP2' logic (page 14)

	//RA[0:3]=0 from prior logic

	//Check initialization
	{Phase1Next'}=0
	RUN101() //for WakeRq_0
	EClock() //TranPh1_0
	WCompare({WakeP3'},1,12400)

	EClock() //TranPx_0
	WCompare({WakeP2'},1,12401)

	//Write "SetWake=1" code into LAddr[0:3]=0
	RamCycA(#54000) //WakePending_(WakeRq=0) in Phase2 (for prom h7 address bit)

	for i = 0 to 1 do
	[
		{Phase1Next'}=i

		RUN101() //Phase1: WakeRq_0
		RClock() //Phase0: read "SetWake=1" code from RA[0:3]=0
		RClock() //Phase3: (redundant write into LAddr[0:3]=0)
		WCompare({SetWake},1,12410+i) //confirm SetWake=1 (prom h7 address = 1010 x00x)

		//WakeRq=0 cases:
		EClock() //TranPh1_0, TranPx_(TranPh1 + TranPx.Phase1Next')
		WCompare({WakeP3'},1,12420+i) //TranPh1=0
		WCompare({WakeP2'},(not i)&1,12430+i) //TranPx=i (from TranPh1=i)

		RClock() //Phase2: WakePending_(WakeRq=0)
		         //        WakeRq_(SetWake=1)

		//WakeRq=1 cases:
		EClock() //TranPh1_i', TranPx_(TranPh1 + TranPx.Phase1Next')
		WCompare({WakeP3'},i,12440+i) //TranPh1=i'
		WCompare({WakeP2'},(not i)&1,12450+i) //TranPx=i (from (TranPx.Phase1Next')=i)
	]

	//Check the remaining input configuration to gate b6a
	{Phase1Next'}=0
	EClock() //TranPx_(((TranPh1=0) + (TranPx=1).(Phase1Next'=0)) =0)
	WCompare({WakeP2'},1,12460) //TranPx=0


//PART 6: Check that the WakeRq holding term (gate a10b - page 11) functions properly

	//{WakeRqHold: Cycle0Feed',Abort',Suspend-a}

	for i = 0 to 15 do
	[
		let x = #54000 % i
		RamCycA(x) //Phase3: write "SetWake=1" code into LAddr[0:3]=i
		RamCycA(x) //Phase1: WakeRq_0 (due to RUN101)
		           //Phase0: WakePending_(WakeRq=0)
		           //        read "SetWake=1" code from RA[0:3]=i
		           //Phase2: WakeRq_(SetWake=1) (prom h7 address = 1010 x00x)

		//Render the gate a10b inputs =i
		{R_DBSB'} = (not i) rshift 3
		ClockCycle0() //R_TimerDly _ i[12]
		{WakeRqHold} = i xor 1; //(Cycle0',Abort',Suspend') _ i[13:15]

		RClock() //Phase1: WakeRq_(WakeRq=1) until i=15 when gate a10b output=0
		         //        RA[0:3]_RA[0:3]+1 (i.e. RA[0:3]_i)
		RClock() //Phase0: WakePending_WakeRq
		WCompare({WakePending},(#77777 rshift i)&1,12500+i) //for test WakeRq
 
		//Complete the Ram cycle to prepare for next pass
		{WakeRqHold}=6; //restore to normal for GoCycle1_1
		RClock() //Phase3: NewCmd_1 (since GoCycle1=1)
		RClock() //Phase2: LoadAdd_(NewCmd=1)
	]
]


//Routine to load RingState[0:3]' and RingDat[0:7]' using RamAddr[0:3]=LAddr[0:3]
//Must be preceded by routine setting Phase1=1, LoadAdd=1, and F1=#22 (i.e. TLoad'=0)

and RamCycA(sda) be //sda feeds: LState[0:3],,LDat[0:7],,LAddr[0:3]
[
	{ALUA}=sda
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1; //clkTimer': LState[0:3]_(ALUA[0:3]   =sda[0:3])
	                    //           LDat[0:7]  _(ALUA[4:11]  =sda[4:11])
	                    //           LAddr[0:3] _(ALUA[12:15] =sda[12:15])
	                    //           LoadCmd_1

	{RUN}=0; //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
	         //"DCreset": WakeRq_0, NewCmd_1, Phase0_1
	{RUN}=1; //return to normal

	//LoadAdd=1, hence: WState[0:3]=LState[0:3],
	//                  WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]=f7 ff's)

	{RamClockFeed'}=0;  //Phase0=1
	{RamClockFeed'}=1;  //ReadClk' : g4 ff's  _(WState[0:3] = sda[0:3])
	                    //           g4,i4 ff's _(WDat[0:7] = sda[4:11])
	                    //           load RingState[0:3]', RingDat[0:7]' from RA[0:3]
	                    //           dlyLoadAdd_(LoadAdd=1)
	                    //           LoadAdd_0 (since Ph0=0)

	{RamClockFeed'}=0;  //Phase3=1
	                    //RingWrt' is active (since dlyLoadAdd=1 and Ph1=1)
	                    //RingWrt' : RAM(LAddr[0:3]=sda[12:15])_(g4,i4 ff's = sda[0:11])
	{RamClockFeed'}=1


	{RamClockFeed'}=0;  //Phase2=1
	{RamClockFeed'}=1;  //ReadClk' : RingState[0:3]'_(RAM(LAddr[0:3]=sda[12:15)' = sda[0:3]')
	                    //           RingDat[0:7]'  _(RAM(LAddr[0:3]=sda[12:15)' = sda[4:11]')
	                    //           dlyLoadAdd_(LoadAdd=0)
	                    //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
	                    //RamClock': Phase1_1

]


//General purpose Ram Cycle dependent on prior control

and RamCycB() be 
[
	{RamClockFeed'}=0;  //Phase1=1
	{RamClockFeed'}=1;  //conditional write (address = RA[0:3])
	                    //RA[0:3]_RA[0:3]+1

	{RamClockFeed'}=0;  //Phase0=1
	{RamClockFeed'}=1;  //read from RA[0:3] (just incremented)

	{RamClockFeed'}=0;  //Phase3=1
	{RamClockFeed'}=1;  //conditional write (address = LAddr[0:3]) 

	{RamClockFeed'}=0;  //Phase2=1
	{RamClockFeed'}=1;  //read from LAddr[0:3], Phase1_1
]