//**************************************************************************************
//MISC5.TST
//By C. Thacker and M. Thomson  						October 6, 1978
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//Test clip from location h7 to tester socket "D":

	//{promh7in: RingState.0',RingState.1',  RingState.2',RingState.3',TestBit,  RingDat.0',WakePending,RingDat=0'}

	//{promh7out: Sample,  Send,SetWake,SetCarry}

//**************************************************************************************
//Test 11: Test the TIMER arithmetic logic (pages 11-14)

let Test11() be
[
	SpeakTest(11) //set initial conditions (see notes at end of MISC.TEST)

//Initialization:

	//RUN=0 during SpeakTest caused: Phase0_1, WakeRq_0, NewCmd_1
	//F2=0 from SpeakTest (hence Rshift=0 since F2 not =#20); also, Cycle0=0
	//From previous test: dlyLoadAdd=0, LoadAdd=1
		//TimerDly=1 for a10b gate output =0 (page 11)
		//RA[0:3]=#17

	{R_DBSB'}=0; //for R_Timer _1 (since Rshift=0)
	{F1}=#22; //for TLoad'_0


//PART 1: Test WDat[0:7] = (RingDat[0:7] = i2 gates) + (Ldat[0:7] = f7 ff's)

	for i = 0 to 15 do
	[
		let a = (((i lshift 4) % i) lshift 4) % #17
		//in notes below: "a" means bits [4:11] of a

		{ALUA}=a
		EClock() //clkTimer': LDat[0:7]_(ALUA[4:11]="a")
		         //           LAddr[0:3]_(ALUA[12:15]=#17)
		         //           LoadCmd_1 (since TLoad'=0)

		RUN101() //Phase1=1 (except on initial entry when Phase1=0)
		         //(Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
		         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

		RClock() //Phase0=1
		         //ReadClk' : g4,i4_(WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]="a"))
		         //           dlyLoadAdd_1, LoadAdd_0

		RClock() //Phase3=1
		         //RingWrt' : RAM(#17)_(g4,i4="a")

		RClock() //Phase2=1
		         //ReadClk' : RingDat[0:7]'_(RAM(#17)'="a"')
		         //           dlyLoadAdd_0, LoadAdd_1

		for j = 0 to 15 do
		[
			let b = ((j lshift 4) % j) lshift 4
			//in notes below: "b" means bits [4:11] of b

			let c = a + b
			let d = (not c) & #4000; //#4000 if msb of (a+b) =0, else 0

			let e = (b xor d) % #140017
			//in notes below: "e" means bits [4:11] of e

			{F1.3}=1; //for F1=#23:
			//TLoad'_1 (for LoadCmd_0), Tadd'_0 (for clkTimer' active)

			{ALUA}=b
			EClock() //clkTimer': LDat[0:7]_(ALUA[4:11]="b")
			         //           LAddr[0:3]_(ALUA[12:15]=0)
			         //           LoadCmd_0 (since TLoad'=1)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			{F1ok}=0; //TLoad'_1 and TAdd'_1, for NewCmd_0 on next RamClock

			RClock() //Phase0=1

		//NOTE: THIS IS THE FUNCTION BEING TESTED
			         //ReadClk' : g4,i4_(WDat[0:7]=(RingDat[0:7]="a")+(LDat[0:7]="b"))
			         //           dlyLoadAdd_1, LoadAdd_0
			         //RamClock': NewCmd_0 (Phase0=1, LoadAdd=1, TLoad'=1, TAdd'=1)

			RClock() //Phase3=1
			         //RingWrt' : RAM(0)_(g4,i4="a+b")

			RClock() //Phase2=1
			         //ReadClk' : RingDat[0:7]'_(RAM(0)'=("a+b")')
			         //           dlyLoadAdd_0, LoadAdd_(NewCmd=0)

		//Check RingDat.0' now since it must always =0 later to check RingDat[1:7]
		//WCompare({RingDat.0'},d rshift 11,11000+i,j)

			//Retrieve the "a" operand from RAM(#17) and add "e" to it.
			//This produces the same sum as ("a+b") except that the msb will always =1

			{F1ok}=1; //restore F1=#23:

			{ALUA}=e
			EClock() //clkTimer': LState[0:3]_(ALUA[0:3]=#14)
			         //           LDat[0:7]_(ALUA[4:11]="e")
			         //           LAddr[0:3]_(ALUA[12:15]=#17)
			         //           (LoadCmd stays =0)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			RClock() //Phase0=1
			         //ReadClk' : dlyLoadAdd_0, LoadAdd_0

			RClock() //Phase3=1 (RingWrt' is inactive since dlyLoadAdd=0)

			RClock() //Phase2=1
			         //ReadClk' : RingDat[0:7]'_(RAM(#17)'="a"')
			         //           dlyLoadAdd_0, LoadAdd_1

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			RClock() //Phase0=1
			         //ReadClk' : g4_(WState[0:3]=LState[0:3]=#14)

		//NOTE: THIS IS THE FUNCTION BEING TESTED
			         //           g4,i4_(WDat[0:7]=(RingDat[0:7]="a")+(LDat[0:7]="e"))
			         //           dlyLoadAdd_1, LoadAdd_0

			RClock() //Phase3=1
			         //RingWrt' : RAM(#17)_(g4,i4=#14,,"a+e")

			RClock() //Phase2=1
			         //ReadClk' : dlyLoadAdd_0, LoadAdd_1

			{F1.3}=0; //for F1=#22:
			//TLoad'_0 (for LoadCmd_1 and clkTimer' active), Tadd'_1

			{ALUA}=a
			EClock() //clkTimer': LDat[0:7]_(ALUA[4:11]="a")
			         //           LAddr[0:3]_(ALUA[12:15]=#17)
			         //           LoadCmd_1 (since TLoad'=0)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			RClock() //Phase0=1 (RamAddr[0:3]=RA[0:3]=#17)
			         //ReadClk' : RingState[0:3]'_(RAM(#17)'=3) (for prom h7 addr.)
			         //           RingDat.0'_(RAM(#17)'=0) (for prom h7 addr.)
			         //           RingDat[1:7]'_(RAM(#17)'=("a+e")'&#177)
			         //           g4,i4_(WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]="a"))
			         //           WakePending_(WakeRq=0) (for prom h7 addr.)
			         //           dlyLoadAdd_1, LoadAdd_0

			RClock() //Phase3=1
			         //RingWrt' : RAM(#17)_(g4,i4="a") (restore for next pass)

			//SetWake=1 since prom h7 address = 0011 x00x

			RClock() //Phase2=1
			         //SetWake=1 => clock the e3,e2 R bus ff's (page 14) as follows:
			         //           r[0:3]_(RingState[0:3]'=3)
			         //           r[4:11]_(RingDat[0:7]="a+e"="a+b"%#200)
			         //           r[12:15]_(RA[0:3]=#17)
			         //ReadClk' : RingDat[0:7]'_(RAM(#17)'="a"')
			         //           dlyLoadAdd_0, LoadAdd_1

		//Check that RingDat[1:7] = ("a+b")&#177 (other bits are constants)
		//WCompare(not {rbus},c % #34017,11100+i,j) //R[0:15] = not r[0:15]

		]
	] 


//PART 2: Test WDat[0:7] = (RingDat[0:7] = i2 gates) + (Ldat[0:7] = f5 gates (DecrRing))

	//Conditions established by prior logic:
	//F1=#22, LoadCmd=1, NewCmd=1, LoadAdd=1, dlyLoadAdd=0, RA[0:3]=#17

	for i = 0 to 1 do
	[
		{ALUA}=#60017 xor (#170037 & (-i)); //#60017 when i=0, #110020 when i=1
		EClock() //clkTimer': LState[0:3]_(ALUA[0:3] = 6 xor -i) (DecrRing when i=1)
		         //           LDat[0:7]_(ALUA[4:11] = i)
		         //           LAddr[0:3]_(ALUA[12:15] = i-1)

		RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
		         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

		RClock() //Phase0=1  (LoadAdd=1, LoadCmd=1)
		         //ReadClk' : g4_(WState[0:3]=LState[0:3] = 6 xor -i)
		         //           g4,i4_(WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]=i))
		         //           dlyLoadAdd_1, LoadAdd_0

		RClock() //Phase3=1  (RamAddr[0:3]=LAddr[0:3]=i-1)
		         //RingWrt' : RAM(i-1)_(g4,i4 = 6 xor -i,,i)

		RClock() //Phase2=1
		         //ReadClk' : dlyLoadAdd_0, LoadAdd_1

		RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
		         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

		RClock() //Phase0=1  (RamAddr[0:3]=RA[0:3] = i-1)
		         //ReadClk' : RingState[0:3]'_(RAM(i-1)' = #11 xor -i)
		         //           RingDat[0:7]'_(RAM(i-1)' = i') 
		         //           dlyLoadAdd_1, LoadAdd_0

		//Change LAddr[0:3] to 1 for mismatch with (RA[0:3] = i-1) in Phase2, 
		//so that a write into RA[0:3] will occur during the following Phase1
		{ALUA}=1
		EClock() //clkTimer': LAddr[0:3]_(ALUA[12:15]=1)

		RClock() //Phase3=1  (RingWrt' is active - don't care (RAM(1)_g4,i4))

	//Check that RingState[0:3]' are correct for DecrRing'=i'
	//WCompare({promh7in}&#360,(#220 xor (-i))&#360,11200+i)

	//Check that the DecrRing' signal = i' (test clip on f5.2 - page 11)
	//WCompare({DecrRing'},(not i)&1,11210+i)

	//Check that the i9 comparator output =0 since RA[0:3] # LAddr[0:3]
	//(test clip on i9.6 - page 13)
	//WCompare({i9p6},0,11220+i)

		RClock() //Phase2=1  (dlyLoadAdd=1, LoadAdd=0)

	
	//NOTE: THIS IS THE FUNCTION BEING TESTED
		         //ReadClk' : g4,i4_(WDat[0:7]=(RingDat[0:7]=i)+(LDat[0:7]=DecrRing=-i))
		         //           i4i ff _0 (since LAddr[0:3]=1) not = (RA[0:3]=i-1))
		         //           dlyLoadAdd_0, LoadAdd_1

		//WCompare({RingDat=0'},2,11321) //FOR TESTING ONLY


		RClock() //Phase1=1  (RamAddr[0:3]=RA[0:3]=i-1)
		//RingWrt' is active since the i4i ff =0
		         //RingWrt' : RAM(i-1)_(g4,i4 = i-i=0)
		         //ReadClk' : RA[0:3]_((RA[0:3]+1)=i)
 		//WCompare({RingDat=0'},2,11322) //FOR TESTING ONLY


		RClock() //Phase0=1
		         //ReadClk' : dlyLoadAdd_1, LoadAdd_0
		//WCompare({RingDat=0'},2,11323) //FOR TESTING ONLY


		RClock() //Phase3=1  (RingWrt' is active - don't care (RAM(1)_g4,i4))
		//WCompare({RingDat=0'},2,11324) //FOR TESTING ONLY


		//Restore LAddr[0:3] to i-1
		{ALUA}=i-1
		EClock() //clkTimer': LAddr[0:3]_(ALUA[12:15]=i-1)
		//WCompare({RingDat=0'},2,11325) //FOR TESTING ONLY


		RClock() //Phase2=1  (RamAddr[0:3]=LAddr[0:3]=i-1)
		         //ReadClk' : RingDat[0:7]'_(RAM(i-1)'=(i-i=0)')
		         //           dlyLoadAdd_0, LoadAdd_1

	//Check that i-i=0 (from the DecrRing' function)
	WCompare({RingDat=0'},0,11300+i)

	
	] 
]