//**************************************************************************************
//MISC4.TST
//By C. Thacker and M. Thomson  						October 6, 1978
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//Test clip from location h7 to tester socket "D":

	//{promh7in: RingState.0',RingState.1',  RingState.2',RingState.3',TestBit,  RingDat.0',WakePending,RingDat=0'}

	//{promh7out: Sample,  Send,SetWake,SetCarry}

//**************************************************************************************
//Test 10: Test the TIMER RAMS and part of the associated logic (pages 11-14)

let Test10() be
[
	SpeakTest(10) //set initial conditions (see notes at end of MISC.TEST)

//Initialization:

	//RUN=0 during SpeakTest caused: Phase0_1, WakeRq_0, NewCmd_1
	//F2=0 from SpeakTest (hence Rshift=0 since F2 not =#20); also, Cycle0=0

	{R_DBSB'}=0; //for R_Timer _1 (since Rshift=0)
	ClockCycle0() //TimerDly_(R_Timer =1) for a10b gate output =0 (page 11)
	{F1}=#22; //for TLoad'_0

	RClock() //Phase0=1
	         //ReadClk' : (dlyLoadAdd_(LoadAdd=?) - don't care)
	         //           LoadAdd_0 (since Ph0=0)
	         //RamClock': NewCmd_1 (since TLoad'=0 and GoCycle1=1)

	RClock() //Phase3=1 (RingWrt' will occur if dlyLoadAdd=1, but is insignificant)

	RClock() //Phase2=1
	         //ReadClk' : dlyLoadAdd_(LoadAdd=0)
	         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
	         //RamClock': Phase1_1
 

//PART 1: Test bits [0:4] of the RAM (g4,h4) using RamAddr[0:3]=LAddr[0:3] (page 13)
//Direct viewing of RingState[0:3]' and RingDat.0' is provided by the h7 test clip

	for i = 0 to 1 do
	[

		//PART 1a: Write into all RAM locations and check what was just written

		for j = 0 to 15 do
		[
			let a = (j*7) rshift 3; //"non-synchronous hex"
			let b = (a xor -i) //invert hex a if i=1
			let c = b&1; //lsb of hex a, inverted if i=1
			let d = (b lshift 4) % (c lshift 2); //for WCompare

			{ALUA} = (b lshift 12) % (c lshift 11) % j
			EClock() //clkTimer': LState[0:3]_(ALUA[0:3] = b)
			         //           LDat[0:7]  _(ALUA[4:11] = c000 0000)
			         //           LAddr[0:3] _(ALUA[12:15] = j)
			         //           LoadCmd_1 (since TLoad'=0)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			//LoadAdd=1, hence: WState[0:3]=LState[0:3],
			//                  WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]=f7 ff's)

			RClock() //Phase0=1
			         //ReadClk' : g4 ff's  _(WState[0:3] = b)
			         //           g4,i4 ff's _(WDat[0:7] = c000 0000)
			         //           dlyLoadAdd_(LoadAdd=1)
			         //           LoadAdd_0 (since Ph0=0)

			RClock() //Phase3=1
			//RingWrt' is active (since dlyLoadAdd=1 and Ph1=1)
			//RamAddr[0:3]=(LAddr[0:3]=j) (since ph0=1)
			         //RingWrt' : RAM(j)_(g4,i4 = b,,c000 0000)

			RClock() //Phase2=1
			         //ReadClk' : RingState[0:3]'_(RAM(j)' = b')
			         //           RingDat[0:7]'_(RAM(j)' = c'111 1111)
			         //           dlyLoadAdd_(LoadAdd=0)
			         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)

			//Check data just written into RAM (address j)
			//WCompare((not {promh7in})&#364,d,10100+i,j) //RingState[0:3]', RingDat.0'
		]


		//PART 1b: Read from all RAM locations to verify addressing integrity

		for j = 0 to 15 do
		[
			let a = (j*7) rshift 3; //"non-synchronous hex"
			let b = (a xor -i) //invert hex a if i=1
			let c = b&1; //lsb of hex a, inverted if i=1
			let d = (b lshift 4) % (c lshift 2); //for WCompare

			{ALUA} = j
			EClock() //clkTimer': LAddr[0:3]_(ALUA[12:15] = j)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			RClock() //Phase0=1
			         //ReadClk' : dlyLoadAdd_(LoadAdd=1)
			         //           LoadAdd_0 (since Ph0=0)

			RUN101() //Phase3=1  (Avoid RingWrt' and go to Phase0)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			RClock() //Phase0=1
			         //ReadClk' : i4i ff _1 (since Phase2=0) (bottom page 13)
			         //           dlyLoadAdd_(LoadAdd=0)
			         //           LoadAdd_0 (since Ph0=0)

			RClock() //Phase3=1 (RingWrt' is inactive since gate b5b output =0)

			RClock() //Phase2=1
			//RamAddr[0:3]=(LAddr[0:3]=j) (since ph0=1)
			         //ReadClk' : RingState[0:3]'_(RAM(j)' = b')
			         //           RingDat[0:7]'_(RAM(j)' = c'111 1111)
			         //           i4i ff _0 (since dlyLoadAdd=0 and Phase2=1)
			         //           dlyLoadAdd_(LoadAdd=0)
			         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)

			//WCompare((not {promh7in})&#364,d,10110+i,j) //RingState[0:3]', RingDat.0'
		]
	]


//PART 2: Set the RA[0:3] address counter to #17 (page 13)


	//PART 2a: Store a constant in all RAM locations for use in PART 2b

	for i = 0 to 15 do
	[
		{ALUA} = #34000 % i
		EClock() //clkTimer': LState[0:3]_(ALUA[0:3]=3)
		         //           LDat[0:3]_(ALUA[4:11]=1000 0000)
		         //           LAddr[0:3]_(ALUA[12:15]=i)

		RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
		         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

		//LoadAdd=1, hence: WState[0:3]=LState[0:3],
		//                  WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]=f7 ff's)

		RClock() //Phase0=1
		         //ReadClk' : g4 ff's  _(WState[0:3] = 3)
		         //           g4,i4 ff's _(WDat[0:7] = 1000 0000)
		         //           dlyLoadAdd_(LoadAdd=1)
		         //           LoadAdd_0 (since Ph0=0)

		RClock() //Phase3=1
		//RingWrt' is active (since dlyLoadAdd=1 and Ph1=1)
		//RamAddr[0:3]=(LAddr[0:3]=i) (since ph0=1)
		         //RingWrt' : RAM(i)_(g4,i4 = 3,,1000 0000)

		RClock() //Phase2=1
		         //ReadClk' : dlyLoadAdd_(LoadAdd=0)
		         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
	]

	
	//PART 2b: Load RAM data and RA[0:3] in R bus reg. (e3,e2 - page 14)

	RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
	         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

	RClock() //Phase0=1
	         //ReadClk' : h2,i3 ff's _RAM(RamAddr[0:3]=LAddr[0:3]=?):
	         //           RingState[0:3]'_(RAM(?)'=#14)
	         //           RingDat[0:7]'_(RAM(?)'=0111 1111)
	         //           WakePending_(WakeRq=0) (for prom h7 addr.)
	         //           dlyLoadAdd_(LoadAdd=1) 
	         //           LoadAdd_0 (since Ph0=0) (for RingDat[0:7]_(not RingDat[0:7]'))

	WCompare({promh7in}&#366,#300,10200) //check that address = 1100 x00x
	WCompare({SetWake},1,10201) //check that prom h7, pin 10 =1
	
	RClock() //Phase3=1, (RingWrt' is active - don't care)

	RClock() //Phase2=1
	         //SetWake=1 => clock the e3,e2 R bus ff's (page 14) as follows:
	         //           r[0:3]_(RingState[0:3]'_#14)
	         //           r[4:11]_(RingDat[0:7]=(not RingDat[0:7]')=1000 0000)
	         //           r[12:15]_(RA[0:3]=?)
	         //ReadClk' : dlyLoadAdd_(loadAdd=0)
	         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)

	//Check the stored constant
	WCompare((not {rbus})&#177760,#144000,10202) //R[0:15] = not r[0:15]


	//PART 2c: Increment RA[0:3] until it is =#17

	let x = (not {rbus}) //RA[0:3] contents =?

	while x ne #17 do
	[
		RClock() //Phase1=1 (RingWrt' is active - don't care)
		         //RamClock': RA[0:3]_RA[0:3]+1 (since Phase1=1)

		RClock() //Phase0=1
		         //ReadClk' : dlyLoadAdd_(loadAdd=1)
		         //           LoadAdd_0 (since Ph0=0)

		RClock() //Phase3=1 (RingWrt' is active - don't care)

		RClock() //Phase2=1
		         //ReadClk' : dlyLoadAdd_(loadAdd=0)
		         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
		x=x+1
	]

	//RA[0:3] should now =#17 and will be incremented only on Phase1 RamClocks


	//PART 2d: Check the RA=LAddr comparator (i9 on page 13)

	for i = 0 to 15 do
	[
		let x = 1 lshift i //for WCompares in j loop

		{ALUA}=i
		EClock() //clkTimer': LAddr[0:3]_(ALUA[12:15]=i)

		for j = 0 to 15 do
		[
			RClock() //Phase1=1 (RingWrt' can be active - don't care)
			         //RamClock': RA[0:3]_RA[0:3]+1 (i.e. RA[0:3]_j)

			RClock() //Phase0=1
			         //ReadClk' : dlyLoadAdd_(loadAdd=1)
			         //           LoadAdd_0 (since Ph0=0)

			//Check the i9 comparator with dlyLoadAdd=1 (output =1 when RA=LAddr)
			//WCompare({i9p6},(x rshift j)&1,10220+i,j)

			RClock() //Phase3=1 (RingWrt' is active - don't care)

			RClock() //Phase2=1
			         //ReadClk' : dlyLoadAdd_(loadAdd=0)
			         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)

			//Check the i9 comparator with dlyLoadAdd=0 (output always =0)
			//WCompare({i9p6},0,10250+i,j)
		]
	]

	//RA[0:3] should now =#17 and will be incremented only on Phase1 RamClocks


//PART 3: Test bits [5:11] of the RAM (h4,h3)
//using both LAddr[0:3] and RA[0:3] for RamAddr[0:3] generation) (page 13)
//Check the RingDat=0' gate (page12)

//The R bus displays the results via the e3 and e2 ff's (page 14)
//Loading of the above R bus ff's requires SetWake=1; this is achieved by
//putting constants in RingState[0:3]' and RingDat.0' (all previously tested) so that
//the h7 prom address wil be 0011 x00x or 1100 x00x

	for i = 0 to 1 do
	[

		//PART 3a: Write into all RAM locations using RamAddr[0:3]=LAddr[0:3]

		for j = 0 to 15 do
		[
			let a = (j*7) rshift 3; //"non-synchronous hex"
			let b = #30000 % (a*#420) //bits [0:11]
			let c = (b xor -i)&#177760 //invert bits [0:11] if i=1

			{ALUA} = c % #4000 % j
			EClock() //clkTimer': LState[0:3]_(ALUA[0:3] = 3 xor -i)
			         //           LDat[0:3]  _(ALUA[4:7] = (a xor -i) % #10)
			         //           LDat[4:7]  _(ALUA[8:11] = a xor -i)
			         //           LAddr[0:3] _(ALUA[12:15] = j)

			RUN101() //Phase1=1  (Avoid RingWrt' and RA[0:3]_RA[0:3]+1)
			         //"DCreset": Phase0_1, WakeRq_0, NewCmd_1

			//LoadAdd=1, hence: WState[0:3]=LState[0:3],
			//                  WDat[0:7]=(RingDat[0:7]=0)+(LDat[0:7]=f7 ff's)

			RClock() //Phase0=1
			         //ReadClk' : g4 ff's _(WState[0:3] = 3 xor -i)
			         //           g4 ff's _(WDat[0:3] = (a xor -i) % #10)
			         //           i4 ff's _(WDat[4:7] =  a xor -i)
			         //           dlyLoadAdd_(LoadAdd=1)
			         //           LoadAdd_0 (since Ph0=0)

			RClock() //Phase3=1
			//RingWrt' is active (since dlyLoadAdd=1 and Ph1=1)
			//RamAddr[0:3]=(LAddr[0:3]=j) (since ph0=1)
			         //RingWrt' : RAM(j)_(g4,i4 = c % #4000)
			         //RamClock': WakeRq_0 (Phase2=0 and gate a10b output =0)

			RClock() //Phase2=1
			         //ReadClk' : dlyLoadAdd_(LoadAdd=0)
			         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
			         //RamClock': i4i ff (bottom page 13) _1 when j=#17,
			         //           since RA[0:3]=LAddr[0:3] and dlyLoadAdd=1 
		]


		//PART 3b: Read out all RAM locations, using RamAddr[0:3]=RA[0:3], then
		//         Write in all RAM locations, using RamAddr[0:3]=LAddr[0:3], then
		//         Read out all RAM locations, using RamAddr[0:3]=LAddr[0:3]
		//         (In all cases RamAddr[0:3] will = j)

		for j = 0 to 15 do
		[
			let a = (j*7) rshift 3; //"non-synchronous hex"
			let b = #30000 % (a*#420) //bits [0:11]
			let c = (b xor -i)&#177760 //invert bits [0:11] if i=1

			{ALUA} = (#20 lshift j) % j
			EClock() //clkTimer': LState[0:3],,LDat[0:7] _ 1 lshift j
			         //           LAddr[0:3]_j (for RA[0:3]=LAddr[0:3])

			RClock() //Phase1=1
			//(RingWrt' is inactive since the i4i ff =1 and dlyLoadAdd=0)
			         //RamClock': RA[0:3]_RA[0:3]+1 since Phase1=1
			         //           WakeRq_0 (since Phase2=0 and gate a10b output =0)

			RClock() //Phase0=1
			         //ReadClk' : RingState[0:3]'_(RAM(j)' = #14 xor -i)
			         //           RingDat[0:3]'_(RAM(j)' = (a' xor -i)&7) 
			         //           RingDat[4:7]'_(RAM(j)' =  a' xor -i) 
			         //           g4,i4 ff's _ 1 lshift j
 			         //           WakePending_(WakeRq=0) (for prom h7 addr.)
			         //           dlyLoadAdd_(LoadAdd=1)
			         //           LoadAdd_0 (since Ph0=0)

			//Check that the prom h7 address = 1100 x00x if i=0 and 0011 x00x if i=1
			//WCompare({promh7in}&#366,(#300 xor -i)&#360,10300+i,j)

			//Check that the above addresses produce SetWake=1 from prom h7, pin 10
			//WCompare({SetWake},1,10310+i,j)

			RClock() //Phase3=1
			//RingWrt' is active (since dlyLoadAdd=1 and Ph1=1)
			//RamAddr[0:3]=(LAddr[0:3]=j) (since ph0=1)
			         //RingWrt' : RAM(j)_(g4,i4 = 1 lshift j)
			         //RamClock': WakeRq_0 (Phase2=0 and gate a10b output =0)

			//RingDat[0:7] = not RingDat[0:7]' (since LoadAdd=0)
 
			RClock() //Phase2=1
			         //SetWake=1 => clock the e3,e2 R bus ff's (page 14) as follows:
			         //           r[0:3]   = RingState[0:3]' = (#14 xor -i)&#17 
			         //           r.04     = RingDat.0       = 1 
			         //           r[5:7]   = RingDat[1:3]    = (a xor -i)&#7
			         //           r[8:11]  = RingDat[4:7]    = (a xor -i)&#17 
			         //           r[12:15] = RA[0:3] = j
			         //ReadClk' : RingDat[0:7]'_(RAM(j)'=(1 lshift j)')
			         //           i4i ff _1 (since RA[0:3]=LAddr[0:3] and dlyLoadAdd=1) 
			         //           dlyLoadAdd_(LoadAdd=0)
			         //           LoadAdd_1 (since NewCmd=1 and Ph0=1)
			         //RamClock': WakeRq_1 (since SetWake=1 and Phase2=1)

			//Check the rbus
			let x = (c xor #170000) % #4000 % j
			//WCompare(not {rbus},x,10320+i,j) //R[0:15] = not r[0:15]

			//Check the RingDat=0' gate (i1 - page 12)
			let y = (not (j rshift 3))&1
				//RingDat=0' =0 when J>7 since RingDat[0:7] = 1 lshift j
			//WCompare({RingDat=0'},y,10330+i,j)
		]
	]
]