//**************************************************************************************
//MISC2.TST
//By C. Thacker and M. Thomson  						January 19, 1979
//Sub Test Program for D0 MISC Module
//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by all MISC test modules:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

//(none)

//**************************************************************************************
//Test 4: Test the CycleControl register (DBX,,MWX) (pages 5,6,7)

let Test4() be
[
	SpeakTest(4) //set initial conditions (see notes at end of MISC.TEST)

	//cc contains DBX and MWX (via test connector from g10 (page 4) to tester socket "B")
	//{cc: DBX.2,DBX.3,  DBX.4,DBX.5,MWX.0-b,  MWX.1-b,MWX.2-b,MWX.3-b}

	//ccr is the high 8 bits of R (DBX[2:5],,MWX[0:3]) (page 7)
	//{ccr: R.00,R.01,  R.02,R.03,R.04,  R.05,R.06,R.07}
	{R_PCXF'}=0; //for R[0:3]_DBX[2:5], R[4:7]_MWX[0:3] when F2 not =#20

	{F2}=#24; //for loadCycleControl and R_PCXF

	//Check CycleControl load and read DBX,,MWX

	for i = 0 to 7 do
	[
		let x = 1 lshift i
		{ALUA}=x
	
		EClock() //for clkXLevel = EdgeClock.GoCycle1.(CycleControl_ +...)
		         //DBX[2:5]_ALUA[8:11], MWX[0:3]_ALUA[12:15]

		//readPCXF since F2 not =#20: R[0:3]_DBX[2:5], R[4:7]_MWX[0:3]
		WCompare({cc}, x,4000+i) //test via g10 test connector
		WCompare({ccr},x,4100+i) //test via rbus
	] 


	//Check that clkXLevel' is disabled properly (ccg = #164 is the "go" state)

	//{ccg: Suspend-a,Cycle0Feed',  Abort',F2ok,F2.0,  F2.1,F2.2,F2.3}

	{ALUA}=#377
	EClock() //MWX_1111, DBX_1111

	{ALUA}=#10; //alter DBX and MWX if illegal clkXLevel' occurs and F2=#24 during loop
	{F2.2}=1; //for F2=#26: loadDB
	EClock() //DB[0:5]_#10 to alter DBX if illegal clkXLevel' occurs and F2 not =#24

	for i = 0 to 7 do
	[
		let x = 1 lshift i
		{ccg} = #164 xor x
		EClock() //probe ccg
		WCompare({cc},#377,4200+i) //DBX and MWX should not change
	]
] 

//**************************************************************************************
//Test 5: Test the Iaddr register (page 1)

and Test5() be
[
	SpeakTest(5) //set initial conditions (see notes at end of MISC.TEST)

	//{iaddr: Iaddr.0,Iaddr.1,  Iaddr.2,Iaddr.3,Iaddr.4,  Iaddr.5,Iaddr.6,Iaddr.7}
	//{ctask: CTask.0,  CTask.1,CTask.2,CTask.3}
	//{ioval: H2.08,H2.09,  H2.10,H2.11,H2.12,  H2.13,H2.14,H2.15}
	//{noioval: BSEL.0,BSEL.1,  F1.0,F1.1,F1.2,  F1.3,LR,LT}

	for i = 0 to 7 do
	[
		let x = 1 lshift i
		let y = (not i) & #377

		for j = 0 to 15 do
		[
			let n = (i lshift 4) % j
			let z = j lshift 4
			{ctask} = j
			{ioval} = x
			{noioval} = y

			{IOInst} = 1; //select ioval % (ctask*16) as Iaddr input
			ClockAd() //load Iaddr
			WCompare({iaddr},x % z,5000,n)

			{IOInst} = 0; //select noioval % (ctask*16) as Iaddr input
			ClockAd() //load Iaddr
			WCompare({iaddr},y % z,5001,n)
		]
	]
]

//**************************************************************************************
//Test 6: Test the PCF and PCX registers (page 8)

and Test6() be
[
	SpeakTest(6) //set initial conditions (see notes at end of MISC.TEST)

	//{PCF: PCF.0,PCF.1,PCF.2}

	//Initialize:
	{R_PCXF'}=0; //for R[8:11]_PCX[0:3], R[12:15]_PCF[0:3] when Rshift=0
	{NewInst'}=0; //NewInst_1 to enable clkPCX'


//Test the PCF[0:3]_(gnd, ALUA[13:15]) function, and
//partially check PCX_PCF and the R[8:15] gates (a7) on page 7

	{F2}=#34; //PCF_' _0 (load PCF); Rshift=0 for R display

//WaitForKey("F2=#34")

	for i = 0 to 7 do
	[
		{ALUA}=i
		EClock() //PCF[0:3]_(gnd, ALUA[13:15]=i)
		WCompare({PCF},i rshift 1,6000,i) //PCF[0:2] edge-pins

		EClock() //clkPCX': PCX_PCF
		WCompare({rbus}&#377,(i lshift 4)%i,6010,i) //R[8:15]_PCX,,PCF
	]


//Test the PCF_PCF+1 function.
//Completely check PCX_PCF and the R[8:15] gates (a7) on page 7.
//Check the NextInstOpTrap logic.

	{ALUA}=0
	EClock() //Load PCF with 0's

	WCompare({PCF},0,6011) //PCF[0:2] edge-pins, JUST TO BE SURE

	for i = 0 to 15 do
	[
		//Check both inputs to gate h16c for NextInstOp'_0 (count PCF)
		{F1}=#36; //NextInst'_0, NextOp'_1; F2ok_0 for inhibit Load PCF

		//WCompare({PCF},7,6012) //PCF[0:2] edge-pins, JUST TO BE SURE
		{F1.3}=i; //NextInst'_1, NextOp'_0 if i[15]=1

		//WCompare({PCF},7,6013) //PCF[0:2] edge-pins, JUST TO BE SURE
		EClock() //PCF_PCF+1 (PCX_PCF, insignificantly)

		//WCompare({PCF},7,6014) //PCF[0:2] edge-pins, JUST TO BE SURE
		{F1ok}=0; //for NextInstOp_0

		//WCompare({PCF},7,6015) //PCF[0:2] edge-pins, JUST TO BE SURE
		EClock() //clkPCX': PCX_PCF; don't count PCF (since NextInstOp=0)

		//WCompare({PCF},7,6016) //PCF[0:2] edge-pins, JUST TO BE SURE
		let a = (i+1)&#17 //value that should be in PCX and PCF

		//WCompare({PCF},7,6017) //PCF[0:2] edge-pins, JUST TO BE SURE

		WCompare({PCF},a rshift 1,6020,i) //PCF[0:2] edge-pins
		WCompare({rbus}&#377,(a lshift 4)%a,6030,i) //R[8:15]_PCX,,PCF

		//Check the NextInstOpTrp logic (page 8)
		WCompare({NextInstOpTrp},(#77600 rshift i)&1,6040,i) //NextInstOp=0

		{F1ok}=1; //for NextInstOp_1
		WCompare({NextInstOpTrp},(#77700 rshift i)&1,6050,i) //NextInstOp=1
 	]


//Test the clkPCX' logic (page 9)
//Status: PCX=0, PCF=0

	//{clkPCXbus: NewInst',Suspend-a,Cycle0Feed'}

	EClock() //PCX_(PCF=0), PCF counts from 0 to 1
	{F1ok}=0; //keep PCF=1

	for i = 1 to 7 do
	[
		{clkPCXbus} = i xor 1; //clkPCX' should stay inactive
		EClock() //don't PCX_(PCF=1), PCX should stay =0
		WCompare({R.11},0,6100,i) //R.11=PCX.3=0
	]
]