//**************************************************************************************
//MISC.TST
//By C. Thacker and M. Thomson  						April 25, 1979
//Main Test Program for UTFP Controller Module
//**************************************************************************************

//NOTE: 1) This test is for rev. J and K S/W and Etch #1 boards or rev. A Etch #2 boards.
//         (See below for prom revisions.)

//      2) New "rev. I" test connectors (defined below) are required for RS232 and PRINTER interfaces.

//**************************************************************************************

//CURRENT PROM REVISION:			key: StitchWeld/Etch#1/Etch#2

//	Rev. C: i11(u116/u114), h11(u115/u113), e9(u131/u129), e8(u132/u130),
//		f9(u133/u131), h7(u36/u37), i6(u35/u36)

//	Rev. C or B: i7(u34/u35)

//	Rev. C or B or A: i13(u83/82), g12(u65/u65), c7(u46/u46), e7(u47/u47),
//		i14(u84/u83), h13(u66/u66), c8(u64/u64), d7(u48/u48), g9(u130/u128),
//		g11(u68/u68), f10(u86/u85), g10(u85/u84), c10(u56/u56), c12(u57/u57),
//		h12(u101/u99), b8(u82/u81), b12(u58/u58), b19(u142/u140)

//**************************************************************************************

//DUMP FILES in ifs-2 under <Thomson>:

//D0MISC-J.DMTESTS contains
//	misc*.tst, misc.d, misc.bp, misc.run, misc*.cm, miscall.cm1, miscall.cm2

//The next two dump files permit modification of the tests

//MISCTESTAUX-J.DM contains
//	misc*.br, misc*.bt, misc.bs, misc.syms

//TEST.DM contains
//	BCPL.RUN, BLDR.RUN, TC.RUN, format.br, testfns,br, SYS.BK, STREAMS.D
//	(tester.d and testdefs.d are not used; misc.d contains their information)

//**************************************************************************************

//***** REMOVE THE R-PACK that terminates PD.0 - PD.7 to run this test !!!! *****
//		Stitch-weld: location b2 (page 10)
//		Etch #1: location u158 (which is between u8 and u9) (page 10)
//		Etch #2: location u30 (page 16)

//**************************************************************************************

//INSTALL THE FOLLOWING TEST CONNECTORS:

//Tester socket "B" to the following:
//	16-pin clip to g10(u85/u84) (standard assembly - corresponding pins)
//		DBX.2:   g10.5,5
//		DBX.3:   g10.6,6
//		DBX.4:   g10.7,7
//		DBX.5:   g10.4,4
//		MWX.0-b: g10.3,3
//		MWX.1-b: g10.2,2
//		MWX.2-b: g10.1,1
//		MWX.3-b: g10.15,15

//Tester socket "C" to the following:
//	16-pin clip to c12(u57/u57) (standard assembly - corresponding pins)
//		c12p1:  c12.1,1
//		c12p2:  c12.2,2
//		c12p3:  c12.3,3
//		c12p4:  c12.4,4
//		c12p5:  c12.5,5
//		c12p6:  c12.6,6
//		c12p7:  c12.7,7
//		c12p9:  c12.9,9
//		c12p10: c12.10,10
//		c12p11: c12.11,11
//		c12p12: c12.12,12
//		c12p15: c12.15,15

//Tester socket "D" to the following:
//	16-pin clip to h7(u36/u37) (corresponding pins)
//		RingState.0': h7.5,5
//		RingState.1': h7.6,6
//		RingState.2': h7.7,7
//		RingState.3': h7.4,4
//		TestBit:      h7.3,3
//		RingDat.0':   h7.2,2
//		WakePending:  h7.1,1
//		RingDat=0':   h7.15,15
//		Sample:   h7.12,12
//		Send:     h7.11,11
//		SetWake:  h7.10,10
//		SetCarry: h7.9,9
//	16-pin clip to i9(u21/u21)
//		i9p6: i9.6,13
//	20-pin clip to f5(u4/u4)
//		DecrRing': f5.2,14

//Tester socket "E" to the following:
//	This is wired to the PRINTER interface plug (defined directly below)
//		PO.5': C131,1
//		PO.6': C133,2
//		PO.7': C135,3
//		DriveOutput': C134,4

//37-pin male D-shell connector (PRINTER interface - page 10)
//	The connector is wired as follows:
//	21 ->  9 (PO.0' ->  PI.0)
//	23 -> 10 (PO.1' ->  PI.1)
//	25 -> 11 (PO.2' ->  PI.2)
//	27 -> 12 (PO.3' ->  PI.3)
//	29 -> 13 (PO.4' ->  PI.4)
//	20 ->470 ohms -> 1 (PO.0 pulls up/down PD.0)
//	22 ->470 ohms -> 2 (PO.1 pulls up/down PD.1)
//	24 ->470 ohms -> 3 (PO.2 pulls up/down PD.2)
//	26 ->470 ohms -> 4 (PO.3 pulls up/down PD.3)
//	28 ->470 ohms -> 5 (PO.4 pulls up/down PD.4)
//	30 ->470 ohms -> 6 (PO.5 pulls up/down PD.5)
//	32 ->470 ohms -> 7 (PO.6 pulls up/down PD.6)
//	32 ->470 ohms -> 8 (PO.6 pulls up/down PD.7)
//	31 -> pin 1 of "x" (see below)  (PO.5')
//	33 -> pin 2 of "x" (see below)  (PO.6')
//	35 -> pin 3 of "x" (see below)  (PO.7')
//	34 -> pin 4 of "x" (see below)  (DriveOutput')
//	"x" is a 16-pin Augat plug.
//	Connecting wires should be 20 inches long.
//	The plug is for Tester socket "E" (directly above).

//25-pin female D-shell connector (RS232 interface - page 15)
//	The connector is wired as follows:
//	 2 ->  3        (TData -> RcvData)
//	 4 ->  5        (ReqSend -> CTS)
//	11 ->  6,15     (RS232SpareOut1 -> DSRdy,TXClockIn)
//	20 ->  8,17,22  (DTermRdy -> CarrierDetect,RCVClockIn,RingIndicator)

//**************************************************************************************

//CHEATING - JUST A LITTLE:
//	There are three elements, feeding Edge Pins, which should really have pullups on them:
//		1) Odata.16 (h19.3 - page 1 - tests  9300+i)
//		2) WakeP3' (a18.6 - page 14 - tests 12420+i, 12440+i)
//		3) WakeP2' (a18.3 - page 14 - tests 12430+i, 12450+i)
//	HOWEVER, they behave as 1's without pullups when in the hi-Z state, therefore
//	the pullups are not entered as REQUIRED at this time.
//	(especially since location h19 requires lifted pins and blue-wires in rev. E-1)

//**************************************************************************************
get "misc.d"

//Edge pin signal busses used by MISC module:

//{ALUA: ALUA.00,  ALUA.01,ALUA.02,ALUA.03,  ALUA.04,ALUA.05,ALUA.06,  ALUA.07,ALUA.08,ALUA.09,  ALUA.10,ALUA.11,ALUA.12,  ALUA.13,ALUA.14,ALUA.15}

//{F1: F2ok,F1ok,F1.0,  F1.1,F1.2,F1.3}

//{F2: F1ok,F2ok,F2.0,  F2.1,F2.2,F2.3}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//**************************************************************************************
//Edge pin signal busses and manifests used by this particular MISC test module:

static
[
	pass = 0
	otime = 0
	exectime = 0
]

//**************************************************************************************
//main program for MISC module test

let main() be
[
	pass = pass+1

	Test1()
	Test2()
	Test3()
	Test4()
	Test5()
	Test6()
	Test7()
	Test8()
	Test9()
	Test10()
	Test11()
	Test12()
	Test13()
	Test14()
	Test15()
	Test16()
	Test17()

]  repeat

//**************************************************************************************
//Routines available for MISC module tests


//16-bit Left-Cyclic-Shift routine
and LCyc(wrd,amount) = valof
[
	resultis((wrd lshift amount)%(wrd rshift (16-amount)))
]


//Wait-Comparison routine
and WCompare(was,sb,testno,drive; numargs na) be
[
	if was eq sb then return

	Ws(FORMATN("*nTest <D>: Was = <B>, Should be = <B>",testno,was,sb))
	if na gr 3 then Ws(FORMATN(", drive = <B>",drive))

	while Endofs(keys) do [  ]  
	Gets(keys)
	Ws("*nRunning...")
]


//"DCreset" routine
and RUN101() be
[
	{RUN}=0
	{RUN}=1
]

//**************************************************************************************
//Clocking routines defined on page 9

and ClockAd() be
[
	let a = {LoadAd'}
	{LoadAd'}=0
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1
	{LoadAd'}=a
]

and ClockCycle0() be
[
	let a = {Cycle0Feed'}
	{Cycle0Feed'}=0
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1
	{Cycle0Feed'}=a
]

and ClockCycle1() be
[
	let a = {Cycle0Feed'}
	{Cycle0Feed'}=1
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1
	{Cycle0Feed'}=a
]
	
and ClockMC2() be
[
	let a = {AdvancePipe'}
	{AdvancePipe'}=0
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1
	{AdvancePipe'}=a
]

and EClock() be  //EdgeClockFeed' is normally high
[
	{EdgeClockFeed'}=0
	{EdgeClockFeed'}=1
]

and RClock() be  //RamClockFeed' is normally high
[
	{RamClockFeed'}=0
	{RamClockFeed'}=1
]

and WaitForKey(msg) be
[
	Ws(msg)
	Ws("  Waiting...")
	while Endofs(keys) do [ ]
	Gets(keys)
	Ws("*nrunning...")
]

//**************************************************************************************
and SpeakTest(testno) be
[

//Calculate the execution time for each test
	let tv=vec 2
	Timer(tv)
	exectime = tv!1 - otime
	otime = tv!1
	Ws(FORMATN("*nExection Time for this test is <D>",exectime))

//Set up title display
	Ws("*n")
	Ws("*n")
	Ws(FORMATN("*nMISC TEST (rev. J): Pass <D>, Test <D>...",pass,testno))
	
//Set up miscellaneous initial conditions
	{ALUA}=0
	{rbus}=###; //open rbus
	{RUN}=0; //reset PAbort (page 2), set RS232OutBit (page 14)
	         //reset d4 flip-flops (page 11)

//{miscbus1: ALUF.0,  ALUF.1,ALUF.2,ALUF.3,  CTask.0,CTask.1,CTask.2,  CTask.3,H2.08,H2.09,  H2.10,H2.11,H2.12,  H2.13,H2.14,H2.15} 16 bits
	{miscbus1}=0

//{miscbus2: BSEL.0,  BSEL.1,F1ok,F1.0,  F1.1,F1.2,F1.3,  F2ok,F2.0,F2.1,  F2.2,F2.3,LR,  LT,RPByte0,RPByte1} 16 bits
	{miscbus2}=0

//{miscbus3: EmRef,  EnableRDlyd2,GateALUParity,IOInst,  LoadMIR,MC1Compa,MC1Compb,  MC2Compa,MC2Compb,MemInst-a,  Plus24,RMOD/d,RSEL.2/d,  RSEL4and5/d,SRC/DEST=0',Suspend-a} 16 bits
	{miscbus3}=0

//{miscbus4: Abort',  AdvancePipe',BPC-Refill',Cycle0Feed',  LoadAd',MC1Active',MC2Active',  MemInst/d',NewInst',Phase1Next',  RSEL.0/d',RSEL.1/d',StartFault'} 13 bits
	{miscbus4}=#17777

//{miscbus5: EdgeClockFeed',RamClockFeed',RUN,  R_DBSB',R_NBR',R_PCXF'} 6 bits
	{miscbus5}=#77
]

//SUMMARY OF THE INITIALIZATION SEQUENCE ABOVE:
	//all input edge-pins are accounted for
	//active high input signals are rendered =0
	//active low  input signals are rendered =1
	//the rbus is in the high impedance state