//**************************************************************************************
//MEMC2.TST
//By B. Rosen and M. Thomson  						December 5, 1978
//Sub Test Program for D0 MEM Module
//**************************************************************************************
get "memc.d"

//Edge pin and test connector signal busses available to this sub-test:

//{Idata: Idata.00,  Idata.01,Idata.02,Idata.03,  Idata.04,Idata.05,Idata.06,  Idata.07,Idata.08,Idata.09,  Idata.10,Idata.11,Idata.12,  Idata.13,Idata.14,Idata.15}

//{Mapbus: LogSngErr,  WriteProtect,Dirty,Referenced,  Map.04,Map.05,Map.06,  Map.07,Map.08,Map.09,  Map.10,Map.11,Map.12,  Map.13,Map.14,Map.15}

//{Mapcon1: MapCAS',  MapRAS',MapRAS',MapCAS',  MC1Ref',MC1Store',MapWrite',  MapCAS',MC1Ref',MC1Store',  MapWrite',MapRAS',MapCAS',  MapCAS',MapCAS',MapRAS'}

//{Mapcon2: EdgeClockFeed',  EdgeClockFeed',EdgeClockFeed',EdgeClockFeed',  WriteProtect,Dirty,Referenced,  MapCAS',MapCAS',MapRAS'}

//{StorA: StorA0,  StorA1,StorA2,StorA3,  StorA4,StorA5,StorA6}

//{StorOut': StorOut.00',  StorOut.01',StorOut.02',StorOut.03',  StorOut.04',StorOut.05',StorOut.06',  StorOut.07',StorOut.08',StorOut.09',  StorOut.10',StorOut.11',StorOut.12',  StorOut.13',StorOut.14',StorOut.15'}

//**************************************************************************************
//Test 3: Test the Map Memory

//        THIS TEST IS STILL BEING DEVELOPED!
//        At present it is functional to a limited extent.
//        Addressing integrity cannot be checked due to timing considerations; however,
//        the data bits appear to be testable.
//        THE TEST HAS BEEN ARRANGED to handle BOTH the S/W and P/C boards; this is
//        controllable as per the LEFT-JUSTIFIED notes below (in loop)


let Test3() be
[
	SpeakTest(3) //set initial conditions (see notes at end of MEMC.TEST)

//SpeakTest initialized the following signals used by this test:

	//MapRAS',MapCAS',MapWrite',MC1Ref',MC1Store' all =1 (Map outputs are at hi-Z)
	//EnRowAd'=1 to disable the StorA[0:6]_Map[9:15]' inverters (page 7)
	//H4_Imux=1 and IMux_Cdat=0 for H4[0:15]_IMux[0:15]_Idata[0:15]
	//ALUF[0:3] = #17 for prom b11 addr = 1111x (ALUF.3 modifies this later)
	//MOBounds=0 for prom i7 addr = xx0x xxx1 (other bits are controlled later)

	let Mapout,was,sb,Mapxor = 0,0,0,0

//Test Write-Read #125252 and #52525 for i = 000-255 (using all Column/Row sets)
//Test Write-Read #135252 and #72525 for i = 256-259 (i.e. merge StorAccessType=1
//with H4[2:3] for Dirty and Referenced =1 (page 8))

	let a = #52525 //Write-Read data
	let x = 0 //initialize error counter
	let y = 0 //count after which errors will cause stop *********

	for i = 0 to 259 do
	[
		a = not a

		{Idata} = a; //for H4[0:15]_IMux[0:15]_(Idata[0:15]=a)
		{ALUF.3} = i<<w.b7; //for StorAccessType_i[7] (via proms b11 and i7 (page 15))
		{Mapcon2} = #177207; //sequence of action as follows:
			//Disable MAP outputs
			//WriteProtect,Dirty,Referenced_000 (stabilize prom i7 address lines)
			//EClock: H4[0:15]_IMux[0:15]_(Idata[0:15]=a)
			//        ClockAd': MC1Ftype.0_0    if prom b11 addr = 1110x (ALUF.3=0)
			//                  MC1Ftype.0_1    if prom b11 addr = 1111x (ALUF.3=1)
			//                  MC1Ftype.1_0 since prom b11 addr = 111xx
			//EClock: StorAccessType_(prom i7)_(MC1FType.0=i[7])
			//        (prom i7 addr = 000x y001, where y controls StorAccessType)
		{Mapbus} = ###; //Disconnect tester drivers from Map memory outputs

	//Check the Map input data (this hardware has been tested previously)
		WCompare({StorOut'},not a,3000,i) //verify H4[0:15] data via StorOut[0:15]'
		WCompare({StorAccessType},i<<w.b7,3001,i) //verify StorAccessType=i[7]

		{StorA} = i rshift 1; //Do all Column/Row sets (with #125252, then with #52525)

	//This step "wakes up" the rams; without it the test will fail
		{Mapcon1} = #37017; //Write-Read cycle

	//The next two steps average 1.4 milliseconds execution time
		{Mapcon1} = #37017; //Write-Read cycle
		Mapout = {Mapbus}; //grab data quickly to minimize refresh problems

//STITCH-WELD BOARDS ONLY - this option HAS NOT been selected ********
		//Mask out the Dirty and Referenced bits since the SloMC1Store' and SloMC1Ref'
		//signals are floating in S/W modules (SPLAT i1 is pulled) (page 12)

		//was = Mapout & #147777
		//sb  = a & #147777

//PRINTED-CIRCUIT BOARDS ONLY - this option HAS been selected ********
		//No masking is required since SloMC1Store' and SloMC1Ref' are connected

		was = Mapout
		sb  = a % (#30000 & (-i<<w.b7)); //merge 1's with Dirty and Referenced when i>255

	//Produce Mapxor and increment error counter if Mapxor not =0
		Mapxor = was xor sb; //MAKES POSITION OF ERROR EASY TO SPOT 
		if Mapxor ne 0 then x=x+1; //ERROR TALLY

	//now test the result
		//IGNORE OCCASIONAL ERRORS WHICH MAY ARISE FROM REFRESH PROBLEMS
		//Will stop if error count > y (y has been set to 0)********

		WCompt3(was,sb,3002,i,Mapxor,x,y) //SEE NOTES ABOVE
	]
]


//Special Wait-Comparison routine peculiar to this test
and WCompt3(was,sb,testno,drive,Mapxor,x,y) be
[
	if was eq sb then return
	if x le y then return

	Ws(FORMATN("*nTest <D>: Mapbus was <B>, should be <B>, drive = <B>",testno,was,sb,drive))
	Ws(FORMATN("*nWAS xor SB = <B>, <D> failures in <D> passes...",Mapxor,x,drive+1))

	while Endofs(keys) do [ ]
	Gets(keys)
	Ws("*nRunning...")
]

//**************************************************************************************
//Test 4: Continue Map Memory Test

and Test4() be
[
	SpeakTest(4) //set initial conditions (see notes at end of MEMC.TEST)

	Ws("*nTesting Map Memory for 90 seconds...")

//Write and Read 0's and 1's using every cell of the Map Memory

	//See Test 3 for initialization notes

	for i = 0 to 1 do //Set up Map write data (Test 3 notes apply)
	[
		let a = -i
		{Idata} = a
		{ALUF.3} = 0; //for StorAccessType_0
		{Mapcon2} = #177207
			//H4[0:15] _ 0 if i=0, #177777 if i=1
			//StorAccessType_0 (for Dirty,Referenced _ H4[2:3])
		{Mapbus} = ###

	for j = 0 to 127 do //Set up Row address to =j
	[
		{StorA} = j
		{Mapcon1} = #157777; //Latch Row address (MapRAS' active)

	for k = 0 to 127 do //Set up Column address to =k; test Write-Read
	[
		{StorA} = k
		{Mapcon1} = #37017; //Write-Read cycle (MapRAS' inactive) ("wake-up")
		{Mapcon1} = #37017; //Write-Read cycle (MapRAS' inactive)
		let Mapout = {Mapbus}; //grab data quickly

		WCompare(Mapout,a,4000+i,(j lshift 9)%k)
		//NOTE: Row and Column addresses are shown in "drive" as follows:
		//      Row address is in left  three octals
		//      Col address is in right three octals
	]
	]
	]
]