//**************************************************************************************
//MEMC1.TST
//By B. Rosen and M. Thomson  						November 22, 1978
//Sub Test Program for D0 MEM Module
//**************************************************************************************
get "memc.d"

//Edge pin and test connector signal busses available to this sub-test:

//{Map.0406: Map.04,Map.05,Map.06}

//{Map.0708: Map.07,Map.08}

//{Mapbus: LogSngErr,  WriteProtect,Dirty,Referenced,  Map.04,Map.05,Map.06,  Map.07,Map.08,Map.09,  Map.10,Map.11,Map.12,  Map.13,Map.14,Map.15}

//{MC1Pipe.0003: MC1Pipe.0,  MC1Pipe.1,MC1Pipe.2,MC1Pipe.3}

//{R.0815: R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{SB.0003: SB0,  SB1,SB2,SB3}

//{SelCard.0007: SelCard0,SelCard1,  SelCard2,SelCard3,SelCard4,  SelCard5,SelCard6,SelCard7}

//{StorA.0006: StorA0,  StorA1,StorA2,StorA3,  StorA4,StorA5,StorA6}

//**************************************************************************************
//Test 1: Check the logic driven by the Map Memory output bits (pages 7,8,11,15)

let Test1() be
[
	SpeakTest(1) //set initial conditions (see notes at end of MEMC.TEST)

//PART 1: Check that the Map outputs are disabled
//        Check for shorts in the Mapbus lines

	//Check that the Map control terms were all raised by SpeakTest
	//{t1bus1: MapCAS',MapRAS',  MapWrite',MC1Ref',MC1Store'}
	WCompare({t1bus1},#37,1000)

	for i = 0 to 15 do
	[
		{Mapbus} = 1 lshift i
		WCompare({Mapbus},1 lshift i,1050+i)
	]

//PART 2: Check the SelCard[0:7] and SB[0:3] logic (page 8)

	//Set prom b11 address to 0011x (SpeakTest sets it to 1111x)
	{ALUF.0}=0; {ALUF.1}=0

	for i = 0 to 15 do
	[

	//Set up Refresh' and Refresh'b to = i[12]' by controllong the prom b11 address (page 15)
	//   i[12]=0 => address=0001x for Refresh'_1
	//   i[12]=1 => address=0011x for Refresh'_0
		{ALUF.2} = i<<w.b12
		EClock() //ClockAd': Refresh'_i[12]', Refresh'b_i[12]'
		WCompare({Refresh'},i<<w.b12 xor 1,1100+i) //verify Refresh'=i[12]'

	//Check the SelCard[0:7] logic (page 8)
		{Map.0406}=i
		let a = ((#200 rshift i) % (-i<<w.b12))&#377
		WCompare({SelCard.0007},a,1200+i)

	//Check the SB[0:3] logic (page 8)
		{Map.0708}=i
		let b = ((#210 rshift i) % (-i<<w.b12))&#17
		WCompare({SB.0003},b,1300+i)
	]

//PART 3: Check R[8:15] _ Pipe Data RAM _ Mapbus[0:7] (page 11)
//        Check StorA[0:6] _ Mapbus[9:15]' (page 7)

	//Set up initial conditions:
	{Disableb9}=1; //for test-clip control of MC1Pipe.0
	{MC1Pipe.0003}=3; //Pipe Data RAM address _3 for RAM_Mapbus[0:7]
	{LoadPipe}=1; //for WritePipe' active when RamClock
	{R_Pipe'}=0; //for R[8:15] _ Pipe Data RAM
	{PreRowAd'}=0; //for EnRowAd'_0
	EClock() //EnRowAd'_(PreRowAd'=0) for StorA[0:6]_Mapbus[9:15]'

	for i = 0 to 15 do
	[
		let a = 1 lshift i
		{Mapbus} = not a
		RClock() //WritePipe': RAM(addr.=3)_Mapbus[0:7]
		EClock() //R[8:15]_d14 ff's_(RAM(addr.=3)'=Mapbus[0:7]')

		WCompare({R.0815},a rshift 8,1400+i) //Mapbus[0:7]' (page 11)
		WCompare({StorA.0006},a&#177,1500+i) //Mapbus[9:15]' (page 7)
	]
]

//**************************************************************************************
//Test 2: Test the i7 prom and associated logic (pages 8,14,15,16)

//NOTE: This test is tricky since three of the prom i7 address bits can only be
//indirectly controlled via the b11 prom and the b9 flip-flops due to test clip limitations.
//The bits are: MC1Pipe.0, MC1Ftype,0, and MC1Ftype.1.
//MC1Pipe.0 will be made to toggle once each pass through the i loop below, equalling i[15].
//MC1Ftype[0:1] will count 00-01-10-10, never achieving the 11 state.
//The above scheme tests all usable i7 prom addresses.

and Test2() be
[
	SpeakTest(2) //set initial conditions (see notes at end of MEMC.TEST)

	//This table contains only 128 entries since the ls address bit of prom i7 is logic high
	let promi7tab = table [

		#02;#02;#03;#03;#03;#03;#02;#02; #04;#04;#05;#05;#05;#05;#04;#04;
		#02;#02;#13;#13;#13;#13;#02;#02; #04;#04;#15;#15;#15;#15;#04;#04;
		#02;#02;#03;#03;#03;#03;#02;#02; #04;#04;#05;#05;#05;#05;#04;#04;
		#02;#02;#13;#13;#13;#13;#02;#02; #04;#04;#15;#15;#15;#15;#04;#04;

		#02;#02;#03;#03;#13;#13;#02;#02; #04;#04;#05;#05;#15;#15;#04;#04;
		#02;#02;#13;#13;#13;#13;#02;#02; #04;#04;#15;#15;#15;#15;#04;#04;
		#02;#02;#13;#03;#13;#13;#02;#02; #04;#04;#15;#05;#15;#15;#04;#04;
		#02;#02;#13;#13;#13;#13;#02;#02; #04;#04;#15;#15;#15;#15;#04;#04 ]

	//Set up initial conditions:

	{MC1SetFault}=1; //Enable clkMC1Faults' for i9 flip-flops (pages 14,15)
	{preMC1Next.7}=0; //kill gate b of MC1Next.7' (page 16)
		//(gates a and c are killed by MC2WillGetR=0 and QWO=0 from SpeakTest)
	{R_Pipe'}=0; //for R.02_MC1ErA', R.03_MC1ErB' (page 15)

	//Initialize MC1Pipe.0 to =1
	//Prom b11 address = 1111x from SpeakTest (state of NewPipe signal is unknown)
	//Prom b11 address = 11xxx causes NewPipe and MC1Pipe.0 to toggle each ClockAd'

	{PAbort} = {MC1Pipe.0}; //LoadAd_LDisableMC1'_0 if MC1Pipe.0=1 (to kill ClockAd')
	EClock() //MC1Pipe.0=0 => ClockAd': MC1Pipe.0_(MC1Pipe.0=0)' (i.e. MC1Pipe.0_1)
	         //MC1Pipe.0=1 => no ClockAd', hence MC1Pipe.0 stays =1
	WCompare({MC1Pipe.0},1,2000) //verify MC1Pipe.0=1

	for i = 0 to 255 do
	[

	//Set up prom i7 address bits (7 bits,,logic high)
		//WriteProtect,Dirty,MOBounds,Referenced _ i[9:12]
		//ALUF.3_i[13]  for MC1Ftype.0 _ i[13] (via prom b11)
		//ALUF.2_i[14]' for MC1Ftype.1 _(i[14] & i[13]') (via prom b11)

		//{t2bus1: WriteProtect,Dirty,MOBounds,  Referenced,ALUF.3,ALUF.2}
		{t2bus1} = (i xor 2) rshift 1

		{PAbort}=0; //for LDisableMC1'_1, hence LoadAd=1 to enable ClockAd'
		EClock() //ClockAd': b9 ff's _ b11 prom (page 15)
		         //MC1Ftype.0 _ i[13]
		         //MC1Ftype.1 _(i[14] & i[13]')
		         //MC1Pipe.0  _ i[15] (since MC1Pipe.0_MC1Pipe.0')
		{PAbort}=1; //disable ClockAd' to keep MC1Pipe.0 from toggling on next clock

	//Calculate the prom i7 address (all possible usable addresses are generated)
	//(The lsb of the address is logic high, hence the address calculated
	//is actually one half of the actual address)
		let a = i & #164 //bits 9,10,11,13
		let b = (i<<w.b14 & (not i<<w.b13)) lshift 1 //bit 14
		let c = (i<<w.b15 lshift 3) % i<<w.b12 //bits 12 and 15 swap places
		let d = a % b % c //prom i7 address (most significant 7 bits, 8th bit is logic high)

	//Verify as much of the prom i7 address as possible (MC1Ftype[0:1] can't be tested)
		//{t2bus2: WriteProtect,  Dirty,MOBounds,MC1Pipe.0,  MC1Pipe.0,MC1Pipe.0,Referenced}
		WCompare({t2bus2}&#171,d&#171,2100,i)

	//Set up conditions for the WCompare to check prom i7
		{Idata.02} = i<<w.b8; //for H4.02_i[8] (gate i4a logic - page 8)
		{MC1TestFault} = not i<<w.b8; //for MC1Next.7' logic (page 16)
		EClock() //H4.02_(Idata.02=i[8])
		         //ClkMC1Faults': MC1ErB _ prom i7, pin 11
		         //               MC1ErA _ prom i7, pin 10
		         //               StorAccessType _ prom i7, pin 9

		let e = promi7tab!d xor #16 //prom i7 outputs, adjusted for logic inversions
		let f = e % (e<<w.b15 lshift 4) //add StorAccessType value to left of e
		let g = #30 & (-i<<w.b8) //pini4.3 and MC1Next.7' are both =1 when i[8]=1

		//Check prom i7 outputs (indirectly)
		//i7 pins 5,6,7,4,3,2,1 should = "drive"; pin 15 is logic high

		//{t2bus3: i4pin3,MC1Next.7',  R.03,R.02,StorAccessType}
		WCompare({t2bus3},f%g,2500+i,d) //see notes above
	]
]