//**************************************************************************************
//MEMB2.TST
//By B. Rosen and M. Thomson  						October 30, 1978
//Sub Test Program for D0 MEM Module
//**************************************************************************************
get "memb.d"

//Edge pin and test connector signal busses available to this sub-test:

//{MC2bus1: MC2NeedsR',MC2NeedsRIfSNE0,  MC2Hold',MC2HoldIfSNE0,MC2TestDE,  MC2TestSE,ALUF.0,ALUF.1,  ALUF.2,ALUF.3,MC2Next.4,  MC2Next.5,MC2Next.6,preMC2Next.7}

//{MC2Next: MC2Next.0,MC2Next.1,  MC2Next.2,MC2Next.3,MC2Next.4,  MC2Next.5,MC2Next.6,MC2Next.7'}

//{MC2out1: MC2Next.0,MC2Next.1,  MC2Next.2,MC2Next.3,MC2Next.4,  MC2Next.5,MC2Next.6,preMC2Next.7}

//{MC2out2: MC2TestSE,MC2TestDE,  MC2HoldIfSNE0,MC2SetFault,ChkPhase0',  LoadSyndrome,preLoadOdata',MC2StartXport}

//{MC2out3: MC2Hold',  MC2WriteCdat,MC2NeedsR',MC2NeedsRIfSNE0}

//**************************************************************************************
//Test 3: Test the MC2 Control Memory address bits and their decodes (page 20)

let Test3() be
[
	SpeakTest(3) //set initial conditions (see notes at end of MEMB.TEST)

	for i = 0 to 7 do
	[
		let a = 1 lshift i

		//set up MC2 address control functions:

			//MC2TestSE,MC2TestDE,MC2HoldIfSNE0 _0 to kill gates a,b,c of MC2Next.7'
			//MC2NeedsR_1, MC2NeedsRIfSNE0_0 to keep MC2WillGetR=0, 
 			//	hence MC2HasR'=1, TypeLoaded=1, and LoadAd=1 
 			//MC2Hold'_1 to keep MC2SynReady=1 and MC2NotReady=0, 
 			//	hence LDisableMC1'=1, AdvancePipe'=0, and LaodAd'=0 

		{MC2bus1} = a xor #24001; //set up functions noted above
		EClock() //clkAd': MC1Type[0:3]_(ALUF[0:3]=a[8:11])
		EClock() //MC2Next[0:3]_(MC1Type[0:3]=a[8:11] since AdvancePipe'=0)

		WCompare({MC2Next},a,3000,i)
		WCompare({MC2Active'},(#17 rshift i)&1,3001,i) //1 if a[8:11]=0
		WCompare({ReadD'},(#373 rshift i)&1,3002,i) //0 if a[13]=1
		WCompare({ReadW'},(#375 rshift i)&1,3003,i) //0 if a[14]=1
	]
]

//**************************************************************************************
//Test 4: Test the MC2 Control Memory prom code (page 20)

and Test4() be
[
	SpeakTest(4) //set initial conditions (see notes at end of MEMB.TEST)

	Ws("*nTesting MC2 Control Memory - proms MUST HAVE rev. E or D code!!")

	//Disconnect the tester output drivers from MC2 output signals
	//which are not used as inputs to this test
	{MC2out2}=###
	{MC2out3}=###

	//Enable prom h2 outputs (disabled during SpeakTest)
	{Disableh2}=0; //for valid ChkPhase0' signal (page 20)

	for i = 0 to 255 do
	[
		let a = MC2sb2(i) //special handling for MC2 bits [8:15]

		//set up MC2 address control functions:

			//MC2TestSE,MC2TestDE,MC2HoldIfSNE0 _0 to kill gates a,b,c of MC2Next.7'
			//MC2NeedsR_1, MC2NeedsRIfSNE0_0 to keep MC2WillGetR=0, 
 			//	hence MC2HasR'=1, TypeLoaded=1, and LoadAd=1 
 			//MC2Hold'_1 to keep MC2SynReady=1 and MC2NotReady=0, 
 			//	hence LDisableMC1'=1, AdvancePipe'=0, and LaodAd'=0 

		{MC2bus1} = i xor #24001; //set up functions noted above
		EClock() //clkAd': MC1Type[0:3]_(ALUF[0:3]=i[8:11])
		EClock() //MC2Next[0:3]_(MC1Type[0:3]=i[8:11] since AdvancePipe'=0)

		//Check the MC2 address
		WCompare({MC2Next},i,4000,i)

		//Check ChkPhase0' (direct output from prom h2 - MC2 "bit 12")
		WCompare({ChkPhase0'},a<<w.b12,4001,i)

		{MC2Hold'}=0; //for AdvancePipe'_1 (gates MC2Next[0:3]_prom g3)
		EClock() //Load MC2 output flip-flops

		{MC2bus1}=###; //Disconnect tester output drivers from MC2 flip-flop outputs
		{DisableMC2}=0; //Enable MC2 flip-flop outputs


		//Check bits [0:7] of MC2 (proms g3 and g1 - page 20)
		WCompare({MC2out1},MC2sb1(i),4002,i)

		//Check bits [8:11] and [13:15] of MC2 (proms h1 and h2 - page 20)
			//MC2StartXport = inverted h3.9 (page 20)
		WCompare(({MC2out2} xor 1)&#367,a&#367,4003,i) //exclude bit 12 (checked in test 4001)

		//Check bits [16:19] of MC2 (prom i2 - page 20)
		WCompare({MC2out3},MC2sb3(i),4004,i)

		{DisableMC2}=1; //Disable MC2 flip-flop outputs
	]
]


and MC2sb1(i) = valof
[
	let locp = mc2+(4*i) //look at "defined" bit
	if ((locp!3)& 1) eq 0 then resultis #377
	resultis locp>>mcblock.firstbyte //left byte of first word
]


and MC2sb2(i) = valof
[
	let locp = mc2+(4*i) //look at "defined" bit
	if ((locp!3)& 1) eq 0 then resultis #377
	resultis locp>>mcblock.secondbyte //right byte of first word
]


and MC2sb3(i) = valof
[
	let locp = mc2+(4*i) //look at "defined" bit
	if ((locp!3)& 1) eq 0 then resultis #17
	resultis locp>>mcblock.fifthhex //left hex of second word
]