//**************************************************************************************
//MEMA3.TST
//By B. Rosen and M. Thomson  						February 1, 1979
//Sub Test Program for D0 MEM Module
//**************************************************************************************
get "mema.d"

//Edge pin and test connector signal busses available to this sub-test:

//{CrctSyn: CrctSyn0,CrctSyn1,  CrctSyn2,CrctSyn3,CrctSyn4,  CrctSyn5,CrctSyn6,CrctSyn7}

//{Odata: Odata.00,  Odata.01,Odata.02,Odata.03,  Odata.04,Odata.05,Odata.06,  Odata.07,Odata.08,Odata.09,  Odata.10,Odata.11,Odata.12,  Odata.13,Odata.14,Odata.15}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{StorDin: StorDin.00,  StorDin.01,StorDin.02,StorDin.03,  StorDin.04,StorDin.05,StorDin.06,  StorDin.07,StorDin.08,StorDin.09,  StorDin.10,StorDin.11,StorDin.12,  StorDin.13,StorDin.14,StorDin.15}

//{StorEcIn: StorEcIn.0,StorEcIn.1,  StorEcIn.2,StorEcIn.3,StorEcIn.4,  StorEcIn.5,StorEcIn.6,StorEcIn.7}

//**************************************************************************************
//Test 5: Test assorted logic indicated by the sub-titles

let Test5() be
[

	SpeakTest(5) //set initial conditions (see notes at end of MEMA.TEST)

//Test the R.04_H4ParityError_H4InputPE_H3IParity_Idata.16 path (pages 1,10,15)

	//{t5bus1: Idata.00,Idata.01,Idata.16}

	//Set up intitial conditions:
	{EnInputParChk}=1; //for H4ParityError_H4InputPE
	{ResetMemErrs'}=0; //Enable RERa' when RamClock
	{MC1SXport}=1; //Enable clkH4Par'
	{R_Pipe'}=0; //for R.04_H4ParityError'
	//SpeakTest sets up the H4_IMux_Idata path; also LoadH3I=1

	for i = 0 to 8 do
	[
		{t5bus1}=i
		EClock() //H4.00_(Idata.00=i[13]) for GenX_i[13]
		         //H4.01_(Idata.01=i[14]) for GenY_i[14]
		         //H4[2:15]_(Idata[2:15]=0)
		         //clkH3I': H3IParity _(Idata.16=i[15])
		RClock() //RERa': DC reset H4ParityError
		WCompare({R.04},0,5000,i)

		EClock() //clkH4Par': H4ParityError_(H4InputPE =1 if i = 0,3,5,6,8)
		WCompare({R.04},(#551 rshift i)&1,5001,i) //If stop, see MEMA.TST, page 1, NOTE 3
	] 

//Test the control logic related to H4ParityError (pages 14,15)

	//H4InputPE=1 from prior logic and will remain =1 during this sub-test

	{EnInputParChk}=0; //disable i16a gate b
	EClock() //clkH4Par': i16a gate a holds H4ParityError =1
	WCompare({R.04},1,5010)

	{ResetMemErrs'}=1; //disable RERa' (page 14)
	RClock() //don't DC reset H4ParityError since RERa' is disabled
	WCompare({R.04},1,5011)
	//[	//test loop
	{ResetMemErrs'}=0; //enable RERa'
	RClock() //RERa': DC reset H4ParityError
	EClock() //i16a gate a holds H4ParityError =0
	WCompare({R.04},0,5012)
	//] repeat	//test loop


	{EnInputParChk}=1; //enable i16a gate b
	{MC1SXport}=0; //disable clkH4Par' (page 14)
	EClock() //don't set H4ParityError since clkH4Par' is disabled
	WCompare({R.04},0,5013)

	{MC1SXport}=1; //return to normal to enable clkH4Par'

//Test the gates which are qualified by H4ParityError

	{preMC1Next.6}=0; //disqualify gate b of MC1Next.6' for loop ahead

	for i = 0 to 3 do
	[

	//Set up H4ParityError = i[14]'
		{Idata.16} = i<<w.b14; //for H3IParity_i[14]
		EClock() //clkH3I': H3IParity_(Idata.16=i[14])
		RClock() //RERa': DC reset H4ParityError
		EClock() //clkH4Par': H4ParityError_(H4InputPE=(H3IParity xor 1)=i[14]')

	//Test the Write' gate (page 13)
		{MC1WriteMem}=i
		WCompare({Write'},(#7 rshift i)&1,5020+i)

		{MC1TestH4Par}=i; //MC1TestH4Par_i[15] for test MC1Next.6' and LDisableMC1'

	//Test gate a of MC1Next.6' (page 16)
		//gate d is disqualified by preMC1Next.6 =0
		WCompare({MC1Next.6'},(#15 rshift i)&1,5030+i)

	//Test gate c of LDisableMC1' (page 18)
		//gates a and b are disqualified by MC2NotReady=0 and PAbort=0
		EClock() //e2b ff_(MC1TestH4Par'=i[15]')

		//Case 1: (e2b ff=i[15]') not = (MC1TestH4Par=i[15])
		WCompare({LDisableMC1'},1,5040+i)

		//Case 2: (e2b ff=i[15]') = (MC1TestH4Par=i[15]')
		{MC1TestH4Par} = not i
		WCompare({LDisableMC1'},(#16 rshift i)&1,5050+i)
	]

//Test the Odata.16 logic (pages 2,3,10,20)

	//Conditions established by SpeakTest:
	//	Udat[0:15]=0 (since StorDin[0:15]=0) (pages 4,5)
	//	UdatParity=0 (since Udat[0:15]=0) (page 2)
	//	Buffer contains 0 (since Udat[0:15]=0) (page 3)
	//	CorrectThisWord=0 (since CrctSyn[4:6]=0) (page 3)
	//	h14h,i,b,c ff's contain 1's (since LoadSyndrome=1) (page 3)

	{StorEcIn.5}=1; //so that StorEcIn.6 can control CorrectThisWord

	//{t5bus2: preLoadOdata',StorEcIn.6,StorDin.15}

	for i = 0 to 8 do
	[
		{t5bus2}=i

		for j = 0 to 6 do EClock()
			//UdatParity__ChkX__Udat.15_(StorDin.15=i[15])
			//CorrectThisWord__CrctSyn.6_ChkSyn.6__(StorEcIn.6=i[14])
			//(Odata.16: h9.1 input)__(CdatParity = (i[14] xor i[15])
			//(Odata.16: h9.2 input)_GateALUParity__Odata_Cdat'__(preLoadOdata'=i[13])

		WCompare({Odata_Cdat'},i<<w.b13,5100,i)
		WCompare({GateALUParity},i<<w.b13,5101,i)
		WCompare({Odata.16},(#771 rshift i)&1,5102,i)
	]

//Test the CorrectThisWord logic via Odata.16 (pages 3,10)

	//Conditions established by previous test:
	//	GateALUParity=Odata_Cdat'=0 (Odata.16 tri-state inverter is enabled) (page 10)
	//	CdatParity=0 (for CdatParity=CorrectThisWord, hence Odata.16=CorrectThisWord')

	//{StorEcIn.0406: StorEcIn.4,StorEcIn.5,StorEcIn.6}

	for i = 0 to 7 do
	[
		{StorEcIn.0406}=i
		EClock() //Partial[4:6]_(StorEcIn[4:6]=i)
		EClock() //CrctSyn[4:6]_(ChkSyn[4:6]=i)

		//Case 1: h14h,i,b,c ff's _(LoadSyndrome=0) for CorrectThisWord=0
		{LoadSyndrome}=0
		for j = 0 to 5 do EClock()
		WCompare({Odata.16},1,5110,i)

		//Case 2: h14h,i,b,c ff's _(LoadSyndrome=1) for CorrectThisWord =1 if i = 3,5,6,7
		{LoadSyndrome}=1
		for j = 0 to 5 do EClock()
		WCompare({Odata.16},(#27 rshift i)&1,5111,i)
	]

//Test the Flip[0:15] logic via Cdat[0:15] and Odata[0:15]

	//Existing conditions:
	//	Odata_Cdat'=0 for Odata[0:15]_Cdat[0:15]
	//	CorrectThisWord=1 (from prior test)

	//{StorEcIn.0300: StorEcIn.3,  StorEcIn.2,StorEcIn.1,StorEcIn.0}

	for i = 0 to 1 do
	[
		//Fill buffer with 0's if i=0 or #177777 if i=1
		{StorDin} = -i
		for j = 0 to 4 do EClock()

		for k = 0 to 15 do
		[
			{StorEcIn.0300}=k; //note that bits [0:3] are in reverse order
			EClock() //ChkSyn[0:3]_(StorEcIn[0:3]=k)
			EClock() //CrctSyn[0:3]_(ChkSyn[0:3]=k)
			         //Flip.0'_0 if k=0....Flip.15'_0 if k=15
			EClock() //Odata[0:3]_(Cdat[0:15] = (Buffer[0:15] xor Flip[0::15]))
			WCompare({Odata},(#100000 rshift k) xor (-i),5120,k)
		]
	]

//Check that LoadSyndrome=0 disqualifies ClockSyndrome' (page 14)
//Check the DC reset term on CrctSyn[0:7] (pages 14,19)

	//LoadSyndrome=1 from SpeakTest

	{StorEcIn}=#377
	EClock() //ChkSyn[0:7]_(StorEcIn[0:7]=#377)
	{StorEcIn}=0
	EClock() //ClockSyndrome': CrctSyn[0:7]_(ChkSyn[0:7]=#377)
	         //ChkSyn[0:7]_(StorEcIn[0:7]=0)

	{LoadSyndrome}=0; //inhibit ClockSyndrome'
	EClock() //don't CrctSyn[0:7]_(ChkSyn[0:7]=0)
	WCompare({CrctSyn},#377,5250) //should remain =#377

	{ResetMemErrs'}=1; //disable RERb' (page 14)
	RClock() //don't reset CrctSyn[0:7]
	WCompare({CrctSyn},#377,5251) //should remain =#377

	{ResetMemErrs'}=0; //enable RERb' (page 14)
	RClock() //RERb': DC reset CrctSyn[0:7]
	WCompare({CrctSyn},0,5252)

	{LoadSyndrome}=1; //restore to normal

//Check the R_Pipe logic not tested elsewhere (pages 15,19)

	//Existing conditions: R_Pipe'=0, CrctSyn[0:7]=0, AdvancePipe=1

	//{R.0007: R.00,R.01,  R.02,R.03,R.04,  R.05,R.06,R.07}

	{ResetMemErrs'}=0
	RClock() //RERa': DC reset MC2ErA, MC2ErB, and FBounds
	WCompare({R.0007}&#307,#300,5300)

	for i = 0 to 1 do
	[
		{MC1Pipe.0}=i; //for MC2Pipe.0_(MC1Pipe.0=i)
		{MOBounds}=i; //for FBounds_(MOBounds=i)

		{MC1SetFault}=0; //inhibit clkMC1Faults'
		{MC2SetFault}=0; //inhibit clkMC2ErA' and clkMC2ErB'
		EClock() //clkStartMC2': MC2Pipe.0_(MC1Pipe.0=i)
		         //don't clock MC2ErA, MC2ErB, or FBounds
		         //CrctSyn[0:7]_(ChkSyn[0:7]=0) for f13,d13 ff's_0 next EClock
		WCompare({R.0007}&#307,#300,5310+i)

		{MC1SetFault}=1; //enable clkMC1Faults'
		{MC2SetFault}=1; //enable clkMC2ErA' or clkMC2ErB'
		EClock() //clkMC1Faults':FBounds_(MOBounds=i)
		         //i=0 => clkMC2ErA': MC2ErA'_1, f13 ff's_(CrctSyn[0:7]=0)
		         //i=1 => clkMC2ErB': MC2ErB'_1, d13 ff's_(CrctSyn[0:7]=0)
		WCompare({R.0007}&#307,(#100 lshift i)%(i lshift 2),5320+i)

		RClock() //RERa': DC reset MC2ErA, MC2ErB, and FBounds
		WCompare({R.0007}&#307,#300,5330+i)
	]

//Check the R[0:7],,R[8:15]_f13,d13 ff's_CrctSyn[0:7] logic (page 19)

	{R_Pipe'}=1
	{ReadSyn'}=0; //for R[0:7]_f13 ff's, R[8:15]_d13 ff's

	//Check that the previous loop caused f13,d13 ff's_(CrctSyn[0:7]=0)
	WCompare({rbus},0,5400)

	for i = 0 to 1 do
	[
		let a = #177400 xor (-i) //#177400 if i=0, #377 if i=1

		{MC1Pipe.0}=i
		EClock() //clkStartMC2': MC2Pipe.0_(MC1Pipe.0=i)

		for j = 0 to 8 do
		[
			let b = #200 rshift j
			let c = (b lshift 8) % b
			{StorEcIn}=b
			EClock() //ChkSyn[0:7]_(StorEcIn[0:7]=b)
			EClock() //CrctSyn[0:7]_(ChkSyn[0:7]=b)
			EClock() //i=0 => clkMC2ErA': f13 ff's_(CrctSyn[0:7]=b), d13's stay =0
			         //i=1 => clkMC2ErB': d13 ff's_(CrctSyn[0:7]=b), f13's stay =0
			WCompare({rbus},a&c,5410+i,j)
		]
	]

	{ReadSyn'}=1; //disconnect f13,d13 ff's from the R bus
]