//**************************************************************************************
//MEMA1.TST
//By B. Rosen and M. Thomson  						January 31, 1979
//Sub Test Program for D0 MEM Module
//**************************************************************************************
get "mema.d"

//Edge pin and test connector signal busses available to this sub-test:

//{Idata: Idata.00,  Idata.01,Idata.02,Idata.03,  Idata.04,Idata.05,Idata.06,  Idata.07,Idata.08,Idata.09,  Idata.10,Idata.11,Idata.12,  Idata.13,Idata.14,Idata.15}

//{Odata: Odata.00,  Odata.01,Odata.02,Odata.03,  Odata.04,Odata.05,Odata.06,  Odata.07,Odata.08,Odata.09,  Odata.10,Odata.11,Odata.12,  Odata.13,Odata.14,Odata.15}

//{rbus: R.00,  R.01,R.02,R.03,  R.04,R.05,R.06,  R.07,R.08,R.09,  R.10,R.11,R.12,  R.13,R.14,R.15}

//{StorDin: StorDin.00,  StorDin.01,StorDin.02,StorDin.03,  StorDin.04,StorDin.05,StorDin.06,  StorDin.07,StorDin.08,StorDin.09,  StorDin.10,StorDin.11,StorDin.12,  StorDin.13,StorDin.14,StorDin.15}

//{StorOut': StorOut.00',  StorOut.01',StorOut.02',StorOut.03',  StorOut.04',StorOut.05',StorOut.06',  StorOut.07',StorOut.08',StorOut.09',  StorOut.10',StorOut.11',StorOut.12',  StorOut.13',StorOut.14',StorOut.15'}

//**************************************************************************************
//Test 1: Check the input busses used by the SpeakTest initialization sequence

let Test1() be
[
	SpeakTest(1) //set initial conditions (see notes at end of MEMA.TEST)


//PART 1: Check that certain flip-flops were properly set in SpeakTest
 
	//Check that R_H3C' and R_H3U' are both =1 (Page 20)
	//MC2XferWord=0 from SpeakTest, hence gates a1b and f2c should both have outputs =1
	WCompare({MC2XferWord},0,1000)
	WCompare({R_H3C'},1,1001)
	WCompare({R_H3U'},1,1002)

	//Check that Odata_Cdat'=0 (Page 20)
	//preLoadOdata'=0 from SpeakTest, hence Odata_Cdat'_e2d ff_(preLoadOdata'=0)
	WCompare({preLoadOdata'},0,1003)
	WCompare({Odata_Cdat'},0,1004)

	//Check that EnColAd'=1 (EnRowAd' should also =1) (Page 13)
	//PreRowAd'=1 from SpeakTest, hence EnColAd',EnRowAd'_(preRowAd'=1)
	WCompare({PreRowAd'},1,1005)
	WCompare({EnColAd'},1,1006)


//PART 2: Manipulate the input busses to detect possible shorts or tri-state disable malfunctions:

	//The following busses correspond to membus1-6 in SpeakTest:

//{t1bus1: Odata_Cdat',  R_H3C',R_H3U',StorA0,  StorA1,StorA2,StorA3,  StorA4,StorA5,StorA6}

//{t1bus2: Disablee2,Disableb9,  Disableh2,DisableMC1,DisableMC2}

//{t1bus3: ALUF.0,  ALUF.1,ALUF.2,ALUF.3,  CTask.0,CTask.1,CTask.2,  CTask.3,StorEcIn.0,StorEcIn.1,  StorEcIn.2,StorEcIn.3,StorEcIn.4,  StorEcIn.5,StorEcIn.6,StorEcIn.7}

//{t1bus4: Cycle0Feed',  MC1XferWord,MC2XferWord,MemInst-a,  MOBounds,ReadSyn',QWO,  RamClockFeed',PAbort,ResetMemErrs'}

//{t1bus5: H4_IMux,LoadH3I,LoadSyndrome,  MC1StartMC2,MC2Hold',MC2NeedsR',  PreRowAd',R_H3I',R_Pipe'}

//{t1bus6: ChkPhase0',  IMux_Cdat,MC1TestH4Par,MC2HoldIfSNE0,  MC2NeedsRIfSNE0,PreloadMC1',preLoadOdata'}

	//The following busses account for all testable tri-state sources not included above:

//{t1bus7: MC1Pipe.1,  MC1Pipe.2,MC1Pipe.3,LoadPipe,  MC1Ref',MC1Store',MC2SetFault,  MC1Next.4,MC1Next.5,preMC1Next.6,  preMC1Next.7,MC1TestFault,MC1SetFault,  MC2WriteCdat,GenPhase0,MapRAS'}

//{t1bus8: MC1NeedsR,MC1WriteR,  MapCAS',MapWrite',MC1SXport,  MC1WriteMem,MC1ClkOutput,EnInputParChk,  MC1Pipe.0,PStore12',MC1TestQWO}

	//Disconnect tester drivers from tri-state outputs which were not disconnected by SpeakTest
	{t1bus5}=###
	{t1bus6}=###
	{t1bus7}=###
	{t1bus8}=###

	//Check the Disable bus separately, emerging from loop with all disables =1

	for i = 0 to 5 do
	[
		{t1bus2} = #7757 rshift i
		WCompare({t1bus2},(#7757 rshift i)&#37,1100+i)
	]

	//Check all busses except R and the Disable bus

	for i = 0 to 16 do
	[
		let a = not (1 lshift i) //use mostly 1's to prevent R-bus input conflicts

		{t1bus1}=a
		WCompare({t1bus1},a&#1777,1200,i)

		{t1bus3}=a
		WCompare({t1bus3},a,1201,i)

		{t1bus4}=a
		WCompare({t1bus4},a&#1777,1202,i)

		{t1bus5}=a
		WCompare({t1bus5},a&#777,1203,i)

		{t1bus6}=a
		WCompare({t1bus6},a&#177,1204,i)

		{t1bus7}=a
		WCompare({t1bus7},a,1205,i)

		{t1bus8}=a
		WCompare({t1bus8},a&#3777,1206,i)

		{Idata}=a
		WCompare({Idata},a,1207,i)

		{StorDin}=a
		WCompare({StorDin},a,1208,i)
	]

	//Check R bus separately while sources in module are disconnected

	for i = 0 to 15 do
	[
		{rbus} = 1 lshift i
		WCompare({rbus},1 lshift i,1300+i)
	]
]

//**************************************************************************************
//Test 2: Check the simple data paths (pages 3,4,5,9,10)

and Test2() be
[
	SpeakTest(2) //set initial conditions (see notes at end of MEMA.TEST)

//Initialization: Disable e2 ff's and let tester control R bus functions (page20)
	{Disablee2}=1
	{R_H3C'}=1
	{R_H3U'}=1
	{Odata_Cdat'}=0

//H4SelIMux (page 18) should = H4_IMux since
	//SpeakTest caused MC2XferWord_0, hence i5.4 gate input _MC2XferingWord_1 

//Cdat is made = BufferOUT by raising CorrectThisWord' (page 3)
	//CorrectThisWord'=1 raises Flip[0:15]' to 1's (page 2) for Cdat = (BufferOUT xor 0)
	{LoadSyndrome}=0; //next 4 EClocks cause CorrectThisWord'_1

	for i = 0 to 15 do
	[
		let a = 1 lshift i
		let b = #100000 rshift i

		{StorDin} = not a
		for j = 0 to 3 do EClock() //Buffer(1st 3 words)_H5(Udat)_(StorDin=a')
		                           //h14c_h14b_h14i_h14h _(LoadSyndrome=0) (page 3)
		                           //CorrectThisWord'_1 for Flip[0:15]_1's
		{StorDin}=a
		EClock() //Advance Buffer (fills with a')
		         //H5(Udat)_(StorDin=a)

		{Idata}=b
		EClock() //H3I_(Idata=b) (ClockH3I' is active since LoadH3I=1 from SpeakTest)
		         //H3C_(Cdat=BufferOUT=a') (see note above re. Cdat)
		         //H3U_(H5(Udat)=a)

		{R_H3I'}=0
		WCompare({rbus},b,2000+i) //H3I
		{R_H3I'}=1

		{R_H3C'}=0
		WCompare({rbus},not a,2100+i) //H3C
		{R_H3C'}=1

		{R_H3U'}=0
		WCompare({rbus},a,2200+i) //H3U

		//For remaining EClocks in loop: rbus=H3U=a and Cdat=BufferOUT=a'

		{Odata_Cdat'}=1; //for Odata_R
		{H4_IMux}=0; //for H4_R (see note above re. H4SelIMux)
		EClock() //Odata_(rbus=H3U=a)
		         //H4_(rbus=H3U=a)
		WCompare({Odata},a,2300+i)
		WCompare({StorOut'},not a,2400+i) //inverted H4
		
		{Odata_Cdat'}=0
		{H4_IMux}=1; //(see note above re. H4SelIMux)
		{IMux_Cdat}=1
		EClock() //Odata_(Cdat=a')
		         //H4_IMux_(Cdat=a')
		WCompare({Odata},not a,2500+i)
		WCompare({StorOut'},a,2600+i) //inverted H4

		{IMux_Cdat}=0; //for IMux_Idata
		EClock() //H4_IMux_(Idata=b), (BufferOUT changes from a' to a - don't care)
		WCompare({StorOut'},not b,2700+i) //inverted H4

		{R_H3U'}=1; //return to inactive state
	]

	//Check that LoadH3I=0 disqualifies ClockH3I'
	{R_H3U'}=1
	{R_H3I'}=0
	{Idata.15}=0
	{LoadH3I}=0
	EClock() //don't H3I.15_(Idata.15=0)
	WCompare({R.15},1,2800) //H3I.15 stays =1
]